SoC Design Engineer(RTL设计)
澜至电子科技
- 公司规模:150-500人
- 公司性质:合资
- 公司行业:电子技术/半导体/集成电路
职位信息
- 发布日期:2019-01-07
- 工作地点:上海-徐汇区
- 招聘人数:1人
- 工作经验:1年经验
- 学历要求:硕士
- 职位月薪:20-40万/年
- 职位类别:集成电路IC设计/应用工程师
职位描述
JOB DESCRIPTION:
1. Module-level architecture definition and design;
2. Module-level RTL implementation;
3. Simulation/Verification at both module level and system level;
4. Module-level synthesis and timing analysis;
5. Writing design spec and report;
6. FPGA/silicon debug on related modules.
JOB QUALIFICATIONS:
1. Bachelor degree or Master degree in ASIC Design Relevant;
2. >2 years of SoC design experience;
3. Solid knowledge on digital IC design; Strong skills of Verilog RTL coding and simulation; Hands-on experiences on EDA tools, such as Cadence and Synopsys tools; Familiar with C language;
4. Relevant experiences on STB product;
5. Good communication skills and Good oral/written English.
职能类别: 集成电路IC设计/应用工程师
公司介绍
联系方式
- 公司地址:地址:span东升街道银河路596号综合楼11楼