(ID51303)principle verification engineer (职位编号：51303)
上海任仕达人才服务有限公司
- 公司性质：合资(欧美)
- 公司行业：专业服务(咨询、人力资源、财会)
职位信息
- 发布日期：2016-09-08
- 工作地点：上海
- 招聘人数：1人
- 工作经验：10年以上经验
- 学历要求：本科
- 职位月薪：15000-20000/月
- 职位类别：其他
职位描述
职位描述：
Roles and Responsibilities
Assume the Technical Leadership role in a Functional Verification team.
Improve existing design verification methodology, tools and flows
Development of UVM Environment, test plan and test benches.
Develop verification plans at module and sub-system level.
Development of Verification Test benches based on
? Coverage driven metrics
? Constrained Random Stimulus generation.
? Assertion based formal checking.
? Property checking / Behavioral model development
Work as one team with other R&D functional teams, define and implement test features required for bring up, debug, validation, characterization, and production.
Assist designers in debug and mentor junior verification engineers
Participate in ASIC and FPGA chip bringup on PCB and in systems
Leverage verification tests for system diagnostic test and production test, where applicable
Qualification Requirement
BS degree with 12 years/MS with 10 years of experience
Strong background in UVM/OVM architecture for verification, functional coverage
Be familiar with Verilog/SystemVerilog, TCL, Perl, C/C++
Be familiar with the simulation tools and flow, e.g. irun, vcs
Demonstrated technical abilities and capable of leading and solving technical challenges. Ability to work cross-functionally.
Energetic. Self-driven. Good communication, organization, analytical, people, project planning, and leadership skills.
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Roles and Responsibilities
Assume the Technical Leadership role in a Functional Verification team.
Improve existing design verification methodology, tools and flows
Development of UVM Environment, test plan and test benches.
Develop verification plans at module and sub-system level.
Development of Verification Test benches based on
? Coverage driven metrics
? Constrained Random Stimulus generation.
? Assertion based formal checking.
? Property checking / Behavioral model development
Work as one team with other R&D functional teams, define and implement test features required for bring up, debug, validation, characterization, and production.
Assist designers in debug and mentor junior verification engineers
Participate in ASIC and FPGA chip bringup on PCB and in systems
Leverage verification tests for system diagnostic test and production test, where applicable
Qualification Requirement
BS degree with 12 years/MS with 10 years of experience
Strong background in UVM/OVM architecture for verification, functional coverage
Be familiar with Verilog/SystemVerilog, TCL, Perl, C/C++
Be familiar with the simulation tools and flow, e.g. irun, vcs
Demonstrated technical abilities and capable of leading and solving technical challenges. Ability to work cross-functionally.
Energetic. Self-driven. Good communication, organization, analytical, people, project planning, and leadership skills.
职能类别： 其他
公司介绍
上海任仕达人才服务有限公司诚聘
联系方式
- Email：recruitmentsh@cn.randstad.com