Principal/Lead Physical Design Engineer
上海芯海集成电路设计有限公司
- 公司规模：150-500人
- 公司性质：民营公司
- 公司行业：电子技术/半导体/集成电路
职位信息
- 发布日期：2014-08-05
- 工作地点：武汉
- 招聘人数：4
- 职位类别：集成电路IC设计/应用工程师
职位描述
Position Description:
？ Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.
？ The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed design. The responsibility includes participating in or leading next generation physical design, methodology and flow development.
？ Ability to handle large sized design implementation tasks alone
Position Requirements:
？ BS degree with 6~10+ years of applicable experience, MS degree with 4~7+ years of applicable experience in electrical engineering, microelectronics.
？ Experienced with ASIC design flow, hierarchical physical design strategies, and methodologies and understand deep sub-micron technology issues. Solid knowledge on LP Design, DFT, static timing analysis, EM/IR-Drop/crosstalk analysis, formal verification, physical verification, DFM. Successful track records of taping out complex, 65/40/28 nm SOC chips.
？ Automation and programming-minded, solid coding experience in Makefile/Tcl/Tk/Perl.
？ Self-motivated, able to work independently or as a team player
？ Excellent verbal and written communication skills in English.