西安招聘

职位描述:

Position Description:
The candidate will be the part of the design team for the development of next generation of video codec IP, the responsibilities include:
1.Micro-architecture definition;
2.Logic implementation with Verilog HDL;
3.Block-level verification;
4.Synthesis and pre-layout/post-layout timing closure;
5.Power analysis and reduction;
6.FPGA prototyping and debugging;

Qualification:
7.BS with 5+ years or MS with 2+ years experiences in electronic engineering/micro-electronics;
8.Expect elf-motivation and team player;
9.Solid skills and rich experiences in logic design, synthesis and timing analysis;
10.Hands-on engineering experiences in video codec development, familiar with video coding standard such like H.264/AVC, MPEG-4, AVS etc.;
11.Familiar with all front-end flows including LINT check, simulation, synthesis, STA, formal and power analysis, etc.;
12.Knowledge and experiences in Computer Architecture and RISC processor (ARM/MIPS/SPARC) micro-architecture would be a great plus;
13.Familiar with AXI4/AXI3 protocol, memory controller would be a plus;
14.Experience in FPGA prototyping and debugging would be a plush;