Senior Backend Engineer
上海芯海集成电路设计有限公司
- 公司规模：150-500人
- 公司性质：民营公司
- 公司行业：电子技术/半导体/集成电路
职位信息
- 发布日期：2013-11-16
- 工作地点：北京
- 招聘人数：2
- 工作经验：五年以上
- 学历要求：本科
- 语言要求：英语
普通话 - 职位类别：集成电路IC设计/应用工程师
职位描述
Title: Senior Backend Engineer
Perform physical design implementation, including synthesis, floor planning, power grid
design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff,
physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure, and physical design
project management.
-The candidate will have the opportunity to work on many varieties of challenging designs,
i.e. low power and high speed design. The responsibility includes participating in or leading
next generation physical design, methodology and flow development.
Position Requirements:
1. BS degree with 10+ years of applicable experience, MS degree with 7+ years of applicable
experience in electrical engineering, microelectronics.
2. Experienced with ASIC design flow, hierarchical physical design strategies, and
methodologies and understand deep sub-micron technology issues.
3. Solid knowledge on LP Design, DFT, static timing analysis, EM/IR-Drop/crosstalk
analysis, formal verification, physical verification, DFM.
4. Successful track records of taping out complex, 65/40/28 nm SOC chips.
5. Automation and programming-minded, solid coding experience in Makefile/Tcl/Tk/Perl.
6. Self-motivated, able to work independently or as a team player, excellent verbal and
written communication skills in English.
Perform physical design implementation, including synthesis, floor planning, power grid
design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff,
physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure, and physical design
project management.
-The candidate will have the opportunity to work on many varieties of challenging designs,
i.e. low power and high speed design. The responsibility includes participating in or leading
next generation physical design, methodology and flow development.
Position Requirements:
1. BS degree with 10+ years of applicable experience, MS degree with 7+ years of applicable
experience in electrical engineering, microelectronics.
2. Experienced with ASIC design flow, hierarchical physical design strategies, and
methodologies and understand deep sub-micron technology issues.
3. Solid knowledge on LP Design, DFT, static timing analysis, EM/IR-Drop/crosstalk
analysis, formal verification, physical verification, DFM.
4. Successful track records of taping out complex, 65/40/28 nm SOC chips.
5. Automation and programming-minded, solid coding experience in Makefile/Tcl/Tk/Perl.
6. Self-motivated, able to work independently or as a team player, excellent verbal and
written communication skills in English.
公司介绍
上海芯海集成电路有限公司专注于成员企业之间的优势互补并加强她们之间的通力合作，从事芯片设计等等方面研发的工程师组成。