武汉招聘

Are you a creative, highly motivated individual with a passion for “doing it right”?

Do you thrive in an environment where delivering customer satisfaction “goes without saying”?

As a Subsystem Implementation CAE in the Solutions Group at Synopsys, you will be responsible for the successful implementation of IP Subsystems involving both digital controller and mixed signal physical layer IPs selected from our broad portfolio of interface IP. You will also work closely with Marketing and R&D teams to collaborate on IP customizations, integration, verification and implementation of IP Subsystems. You will analyze and resolve complex Subsystem usage/implementation issues and provide timely, accurate technical guidance to customers. You will also be responsible for contributing to the authoring of the associated Subsystem documentation such as user guides, application notes and white papers that promote the Subsystems' ease of use, or address specific challenges in its implementation. You will have regular contact with external customers and internal contacts across cross-functional teams. Occasional travel will be required.



Responsibilities

· Lead the planning, co-ordination and execution of complex IP subsystems including the design additional blocks as necessary to meet with the design specification.

· Hands-on RTL design and coding of additional functional logic blocks.

· Debug designs in simulation, emulation and silicon.

· Participate in design specification, verification plan, code and coverage reviews.

· Proactively engaging with customers during integration and silicon debug.



Education and Experience

· Bachelors and/or Master’s Degree in Electrical and/or Electronic Engineering, Computer Engineering or Computer Science.

· Minimum of 10 years relevant experience in ASIC/SoC front-end design including RTL coding in Verilog, logic and clock tree synthesis, static timing analysis, equivalence checking.

· Full understanding of digital design methodologies and tools including formal verification.

· Domain knowledge of one or more of the following protocols:

o DDR - DDR3, DDR4, LPDDR2, LPDDRR3

o PCI Express – Gen2, Gen3

o USB – 2.0, 3.0

· Must have experienced multiple ASIC/SoC tape-outs from concept to full production.

· Excellent analytical and project leadership skills.

· Technically creative, results oriented with the ability to manage multiple tasks efficiently including customer support issues and priorities.

· Strong communication skills and ability to interact with customers as well as peers.

· Adaptability to fast moving, changing environment with constant challenge.

· High degree of self-motivation and personal responsibility.

· Have the ability to work well within a team environment.

Synopsys公司（Nasdaq：SNPS）是为全球集成电路设计提供电子设计自动化（EDA）软件工具的企业。为全球电子市场提供先进的IC设计与验证平台，致力于复杂的芯片上系统（SoCs）的开发。同时，Synopsys公司还提供知识产权和设计服务，为客户简化设计过程，提高产品上市速度。新思公司总部设在美国加州硅谷，有超过60家分公司分布在北美、欧洲、日本与亚洲。
Synopsys,Inc.[Nasdaq:SNPS],headquartered in Mountain View,California,creates leading electronic design automation(EDA)tools for the global electronics market.The company delivers advanced design technologies and solutions to developers of complex integrated circuits,electronic systems and systems on a chip.Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers.
Over the past several years,Synopsys has entered into partnerships with IBM,SGS-Thomson,SEMATEC,Toshiba and others to develop tools and design flows for complex IC and ASIC designs at 0.25 micron and below.The Company has also partnered with programmable logic vendors and other EDA companies to tackle issues ranging from the impact of complex silicon in programmable devices to sound design reuse strategies.

You'd better submit your resume via jobs-china@synopsys.com.