武汉招聘

Job Purpose and Mandate:

This position of “Manager, R&D” is a Mixed-Signal Design Manager focusing on ASIC / Digital Design and Verification. In addition to being a manager of Design and Verification Engineers, the mandate of this role is to act as a project lead and technical lead in the design of semiconductor integrated circuits in compliance with the project’s specifications and Synopsys’ design methodologies. The successful candidate will work on a variety of design and verification tasks, incorporating such tasks as, and not limited to, architecture definition, specification generation, RTL coding, behavioural coding, testbench and testcase generation, RTL simulation, synthesis, STA, gate-level simulation, formal verification, documentation, and prototype evaluation. As a Manager, the successful candidate will also be responsible for recruiting, project staffing, project and staff scheduling, performance reviews and career-path development of staff.

Duties:
Will be responsible for team leadership and project leadership.
Perform staff recruiting, provide staff training, set and monitor staff schedules and goals, and perform annual performance reviews of staff.
Generation of design specifications.
Perform architecture studies for complex digital blocks.
Write synthesizable RTL code for circuit portions of integrated circuits.
Write behavioural models.
Generate testbenches and testcases.
Perform complex RTL simulations of circuits, interpret the results and optimize the code until the predetermined functionality is satisfied.
Generate timing constraints for synthesizable designs.
Perform logic synthesis and/or static timing analysis.
Perform gate-level simulations of circuits, interpret the results and optimize the design until the predetermined functionality and timing is satisfied.
Perform mixed-mode simulations.
Documentation of functionality, code, verification environments/plans, and design procedures.
May participate in prototype evaluation using bench top laboratory instruments or automated test equipment.
Communicate with other Synopsys employees regarding customer technical support.
May communicate directly with customers regarding technical support.
Other related duties as assigned by the manager.
Requirements:
Requires a degree in Engineering or Applied Science (or equivalent) and 5+ years working experience in a related field.
Familiarity with verilog circuit design and design verification.
Previous staff management experience.
Previous Team and/or Project Leadership experience.

Synopsys公司（Nasdaq：SNPS）是为全球集成电路设计提供电子设计自动化（EDA）软件工具的企业。为全球电子市场提供先进的IC设计与验证平台，致力于复杂的芯片上系统（SoCs）的开发。同时，Synopsys公司还提供知识产权和设计服务，为客户简化设计过程，提高产品上市速度。新思公司总部设在美国加州硅谷，有超过60家分公司分布在北美、欧洲、日本与亚洲。
Synopsys,Inc.[Nasdaq:SNPS],headquartered in Mountain View,California,creates leading electronic design automation(EDA)tools for the global electronics market.The company delivers advanced design technologies and solutions to developers of complex integrated circuits,electronic systems and systems on a chip.Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers.
Over the past several years,Synopsys has entered into partnerships with IBM,SGS-Thomson,SEMATEC,Toshiba and others to develop tools and design flows for complex IC and ASIC designs at 0.25 micron and below.The Company has also partnered with programmable logic vendors and other EDA companies to tackle issues ranging from the impact of complex silicon in programmable devices to sound design reuse strategies.

You'd better submit your resume via jobs-china@synopsys.com.