Chip Level PD (Sr/Stuff Engineer)
贵州华芯通半导体技术有限公司
- 公司规模：150-500人
- 公司性质：合资
- 公司行业：电子技术/半导体/集成电路
职位信息
- 发布日期：2016-12-08
- 工作地点：上海-浦东新区
- 招聘人数：5人
- 工作经验：5-7年经验
- 学历要求：硕士
- 职位月薪：20000-40000/月
- 职位类别：高级硬件工程师
职位描述
职位描述：
Position Description
Work with Front-End design team and physical design team for large scale ASIC chip physical implementation. Work on physical design of deep sub-micron Server CPU chips top level (full chip) floorplanning, timing closure, place&route, physical verification etc. Especially focus on top level physical partition, block sizing and shaping, power planning, top level place & routing.
Responsibilities
1. Work on top level physical implementation flow from RTL to post-route, and focus on physical design part: top level physical partition, block sizing and shaping, block port assignment, power planning, top level place & routing.
2. Critical issue resolve on top congestion or timing issues. Overall view and solution made to relief congestion hot spot and fix timing.
3. Evaluate new EDA PR tools and PR methodology best-fitted for current project.
4. Evaluate new process feature based on current project, and help to figure out best top level PR flow.
5. Help block engineers to solve physical issues.
6. Better be expert on one or more aspect like: power/ clock/ PV.
Qualifications
Education and Experience
MSEE with 2+ years or Bachelor with 3+ years of industrial experience of deep submicron digital ASIC design
Skills and Knowledge
1. Good knowledge in following physical design concepts: synthesis, floorplan, place-and-route, timing closure, timing sign-off, DFT, power analysis, hierarchical flow
2. Skilled in the field of IC digital implementation flow and major EDA tools such as DC, ICC/ICC2, EDI/INNOVUS, PT, Redhawk or equivalent
3. Skilled in scripting and building flow automation using Tcl, Perl, Python or equivalent
4. Good listening, writing and speaking English
5. Good communication skills, strong interpersonal skills and the flexibility
6. Plus with 5+ projects tapeout experience
举报
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Position Description
Work with Front-End design team and physical design team for large scale ASIC chip physical implementation. Work on physical design of deep sub-micron Server CPU chips top level (full chip) floorplanning, timing closure, place&route, physical verification etc. Especially focus on top level physical partition, block sizing and shaping, power planning, top level place & routing.
Responsibilities
1. Work on top level physical implementation flow from RTL to post-route, and focus on physical design part: top level physical partition, block sizing and shaping, block port assignment, power planning, top level place & routing.
2. Critical issue resolve on top congestion or timing issues. Overall view and solution made to relief congestion hot spot and fix timing.
3. Evaluate new EDA PR tools and PR methodology best-fitted for current project.
4. Evaluate new process feature based on current project, and help to figure out best top level PR flow.
5. Help block engineers to solve physical issues.
6. Better be expert on one or more aspect like: power/ clock/ PV.
Qualifications
Education and Experience
MSEE with 2+ years or Bachelor with 3+ years of industrial experience of deep submicron digital ASIC design
Skills and Knowledge
1. Good knowledge in following physical design concepts: synthesis, floorplan, place-and-route, timing closure, timing sign-off, DFT, power analysis, hierarchical flow
2. Skilled in the field of IC digital implementation flow and major EDA tools such as DC, ICC/ICC2, EDI/INNOVUS, PT, Redhawk or equivalent
3. Skilled in scripting and building flow automation using Tcl, Perl, Python or equivalent
4. Good listening, writing and speaking English
5. Good communication skills, strong interpersonal skills and the flexibility
6. Plus with 5+ projects tapeout experience
职能类别： 高级硬件工程师
关键字： PD PnR STA
公司介绍
贵州华芯通半导体有限公司
贵州华芯通半导体技术公司由贵州省及美国高通公司共同出资成立，注册地为贵州贵安新区，在北京、上海和贵安新区设有研发运营机构。贵州华芯通半导体专注于设计、开发并销售供中国境内使用的先进服务器芯片。华芯通半导体技术有限公司的成立有助于推动中国集成电路产业发展、提升中国芯片产业开发及设计能力，以及推动并实现中国“强芯梦”。
华芯通半导体2017校园招聘网申地址 http://campus.51job.com/hxt 我们期待你的加入！
贵州华芯通半导体技术公司由贵州省及美国高通公司共同出资成立，注册地为贵州贵安新区，在北京、上海和贵安新区设有研发运营机构。贵州华芯通半导体专注于设计、开发并销售供中国境内使用的先进服务器芯片。华芯通半导体技术有限公司的成立有助于推动中国集成电路产业发展、提升中国芯片产业开发及设计能力，以及推动并实现中国“强芯梦”。
华芯通半导体2017校园招聘网申地址 http://campus.51job.com/hxt 我们期待你的加入！
联系方式
- 公司地址：地址：span贵安新区