天津招聘

职位描述：
Responsibilities:
- Responsible for DFT planning regarding to IP or SoC
- Responsible for implementation and verification for MBIST
- Responsible for implementation and verification for Scan/ATPG
- Responsible for DFT pattern generation, release and ATE bring-up
- Responsible for DFT flow/quality improvements

Requirement:
- Major in CS, EE or related, BSEE required, MSEE preferred
- 2~10 years of hands-on experience in DFT related field
- Strong knowledge of DFT including scan, ATPG, BIST and other DFT methodology
- Strong experience with popular DFT EDA, Mentor DFT solution is preferred
- Knowledge of synthesis, STA is a plus
- Familiar with common UNIX utility such as Shell, Perl, TCL
- Good English communication skills
- Self-motivated and good team player 举报 分享

贵州华芯通半导体有限公司

贵州华芯通半导体技术公司由贵州省及美国高通公司共同出资成立，注册地为贵州贵安新区，在北京、上海和贵安新区设有研发运营机构。贵州华芯通半导体专注于设计、开发并销售供中国境内使用的先进服务器芯片。华芯通半导体技术有限公司的成立有助于推动中国集成电路产业发展、提升中国芯片产业开发及设计能力，以及推动并实现中国“强芯梦”。

华芯通半导体2017校园招聘网申地址 http://campus.51job.com/hxt 我们期待你的加入！