深圳招聘

要求：电子工程硕士，5年左右模拟电路设计，精通TIA, PLL, CDR, LNA, SerDes等高速接口, ToF, Temperature Sensor, High-precision/ High-speed ADC等任一方向, 较好的团队管理经验

坐标：上海张江（Design Manager）/深圳龙岗 (RD Head)

Job Responsibilities:
1. Lead RD team to design, analyze and implement high-performance (>10GHz) PLL, wireline amplifiers, CDR, SERDES, PLL, PAM4, TDCs, TOF, low-noise amplifiers, transmitters, power-amplifiers and power-drivers, or other baseband circuits like LDO, temp sensor, ADC, Filters, etc.

2. The design of high-frequency (multi-gigahertz) and high-precision clocking and analog circuits.

3. Use EDA tools (Cadence, Mentor) to run simulation and function verification.

4. Guide layout engineer to optimize layout.

5. Chip debug and testing individually and with the team.

6. Other tasks assigned by line manager.

Qualifications:
1. MSEE or PhD with at least 5-year experience.
2. Hands-on design experience.

3. Great team management skills.
4. Experience in Cadence EDA tools.
4. Team player with good communication skills.
5.Experience with multi-gigahertz high-speed interface like SERDES transmitter/receiver, or TIA/PLL/CDR/LNA, ToF, Temperature Sensor, high-precision/high-speed ADC or power management IC is highly preferred.
6. Experience in Cadence EDA tools.
7. Team player with good communication skills.

光梓信息科技（上海）有限公司是我国高速光电集成芯片领域内的领军企业之一。公司总部位于上海浦东新区张江高科园区内，由国家领军创新创业团队在国内外***风险投资的支持下创建。光梓科技致力于研发和产业化应用于数据中心、智能传感、5G数据传输的高速低功耗光电子集成芯片。公司利用具有自主知识产权和专利的全CMOS高速低功耗光电子芯片设计和制造技术，联合世界领先水平的研究单位和行业内的龙头企业，为快速增长的云计算大数据中心提供在性能、功耗、价格上都有极强竞争力的高性能核心芯片。