深圳招聘

岗位职责:

？ Work with SOC and system architects to define architecture and design of the DDR controller and subsystem;
？ Perform RTL coding and micro architecture tasks;
？ Support the verification team with verification strategies, debug and coverage closure;
？ Participate in test plan and coverage reviews;
？ Work with Physical design team with physical constraints, timing analysis and signoff responsibilities for DDR controller and subsystem;
？ Participate in the definition of the DDR lab testing and validation of SoC silicon.

任职资格:

？ Solid background and understanding of high-performance memory subsystem architectures and principles. Experience with the latest DDR protocols;
？ Deep understanding of DDR technologies such as DDR3/4/5, lpDDR3/4/4x/5, JEDEC standards;
？ Deep understanding of ARM, CPU/SoC architecture;
？ Experience in implementing DDR controller bring up such as initialization code PHYs training/calibration procedure;
？ Strong knowledge of digital design flow including RTL simulation, logic synthesis, timing constraints, timing closure, gate level simulation, and equivalence checking;
？ Excellent communication skills and teamwork abilities;
？ Familiar with high speed LPDDR IO characterization and PVT qualifications is a plus;
？ Previous experience working with major DRAM memory vendors and validation of DRAM device is a plus.

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