深圳招聘

Junior or Senior

Responsibilities：

1. This position is for a digital-ASIC verification engineer to build next-generation analog/mixed-signal SoC chipsets.

2. Responsible for all aspects of UVM (Universal Verification Methodology), from start to finish. Good knowledge of communication protocols and associated verification IPs (VIPs). Extensive experience with assertions, cover properties, constrained random testing.

3. Work with other digital designers to verify many aspects of ASIC design flow including: architecture, RTL coding/Verification, Synthesis, DFT, STA and P&R (for backend designer).

4. Participate in chip debug, validation, and marketing specifications.

Qualificaitons：

1. MSEE, Junior:2-3 years' verification experience, Senior: 5-6 years' experience.

2. REQUIRED: Experience in metrics-driven verification methodology (System-Verilog/UVM based).

3. Excellent knowledge of ASIC design, such as arithmetic structure (addition, multiplication, interation), timing analysis, DFT, meta-stability, etc.

4. Fundamental understanding of digital signal processing, such as FIR/IIR filter structure, error correction, and decimation.

5. Desired usage experience of mainsteam industry-standard EDA tools, such as VCS/NC, Design Compiler, PrimeTime, Formality/ Conformal and Tetramax/DFT compiler.

6. Experience in other vertical aspects of ASIC design (front-end and back-end) will be a great plus.

7. Experience in perl/python/tcl scripts is a plus.

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