深圳招聘

Responsibilities:

? Work with the global design team to do complex SOC physical implementation for deep submicron design. 

? Participates in block level backend design for complex SOC designs.

? Responsible for RTL to GDS flow including CPF definition, logic/physical synthesis, die size estimation, floor-planning, power planning, CTS, place and route, STA, signal integrity, timing closure, formal verification, DRC/LVS/DFM physical verification etc.

? Play a critical role in high performance design timing closure.

Requirements:

? Bachelor's degree or above in Microelectronics, Electrical Engineering, Computer Science or relevant disciplines.

? Prefer to have basic experience in IC physical implementation.

? Experience using backend EDA tools; i.e. Cadence Genus/Innovus/Tempus, Synopsys DC/ICC2, Mentor Graphics Calibre etc is a plus.

? Relevant experience in the area of digital circuit design is a plus.

?Good knowledge of C/C++, Perl/TCL. Script in Linux/Unix environment is a plus.

? Good language skill in English. Passed CET- 6.

恩智浦半导体（纳斯达克代码：NXPI）致力于通过先进的安全连结及基础设施解决方案为人们更智慧安全、轻松便捷的生活保驾护航。作为全球领先的嵌入式应用安全连接解决方案领导者，恩智浦不断推动着互联汽车、端对端安全及隐私、智能互联解决方案市场的创新。恩智浦拥有超过60年的专业技术及经验，拥有29,000名员工，业务遍及30多个国家，2019年的营业额达88.8亿美元。