深圳招聘

岗位职责:

1. Lead design team to deliver SOC bus RTL, including bus topology, bus fabric, bus monitor, and bus bridge by using Bus generation tool or hand write design.
2. Investigate and research the different aspects of performance, power, latency, QOS and FW/SW support
3. Collect issues identified through system-level evaluation and convey those to the ASIC engineering team, advocating for fixes and/or improvements to the design, where needed.
4. Support firmware and ASIC design engineering teams in the collective effort of device and system level testing.

任职资格:

Minimum Qualifications
1. 9+ years of industry experience of SOC bus design or integration
2. Proven expertise in various bus protocols (AHB, AXI, ACE, ) and network on chip.
3. Expertise in energy-efficient/low-power logic design
4. Strong problem solving to interpret performance analysis and make design tradeoffs.
5. Experienced in system verification FPGA Platform/Emulator/silicon bring up
6. Experienced in RTL design and SOC tapeout flow
7. Strong communication and social skills for working with multi-functional teams.

Preferred Qualifications
1. Experience in DDR design or integration
2. Experience in System cache design or integration
3. Experience in MultiCores design or integration
4. Familiarity with debug infrastructure and CPU architecture is a big plus
5. Experience in frontend implementation tasks such as synthesis, STA, and logic equivalence.
6. Industry exposure to and knowledge of ASIC/FPGA design methodology
7. Familiarity with IP evaluation/selection/license is a plus
8. Familiarity with SOC system architecture is a plus

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