深圳招聘

Responsibility:

Write RTL code for Low power and multi-clock domain designs.

Perform synthesis and pre- and post-layout timing closure.

Run the whole front-end design flow such as Synthesis, power analysis, and Formal check etc.

Contribute test specifications and support evaluation of the design in coordination with application and product engineering.

Provide design documentation, descriptions and information to application engineers, field application engineers, prodsuct engineers, and customers.

Requirement:

Major in EE, CS or related, Master Degree with 2+ years or Bachelor with 4+ years working experiences in ASIC design.

Familiar with Verilog and RTL design

Good problem solving and communication skills

Good written and spoken English. Be able to work together with global team.

Familiar with System-Verilog and UVM verification methodology is a plus

Familiar with script languages(perl,tcl,sh etc.) is a plus

Familiar with STA timing flow is a plus

We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, We go all in with you. Focused and determined, we unite behind your goals as our own. We leverage our unrivaled portfolio of infrastructure technology to identify the best solution for your unique needs. And we sit shoulder-to-shoulder with your teams to build it. Agile in our thinking, and our partnerships, we look for unexpected connections that deliver a competitive edge and reveal new opportunities. At Marvell, we’re driven by the belief that how we do things matters just as much as what we do. Because, with a foundation built on partnership, anything is possible.

Website: **********************