深圳招聘

Job description:
- Individual will work closely with analog/mixed-signal engineers in the floor-plan, layout, and physical design of highly-integrated SoCs.

Qualifications:
- 3-5 years experience with Cadence Virtuoso, Mentor Calibre, Synopsys.
- DRC, LVS, Metal Fill, Tapeouts, Metal Rules, Electromigration, Fringe Cap, Via rules, Matching, Inductance noise, wire resistance.
- Basic understanding of IC design (RLC circuits and Kirchoff’s Law, symmetry, frequency response, transistor matching).
- Desired: Analog layout design (differential symmetry; ground shielding; high-frequency impedances; current returns; noise coupling; transistor parasitics; parasitic fringe capacitances).

光梓信息科技（上海）有限公司是我国高速光电集成芯片领域内的领军企业之一。公司总部位于上海浦东新区张江高科园区内，由国家领军创新创业团队在国内外***风险投资的支持下创建。光梓科技致力于研发和产业化应用于数据中心、智能传感、5G数据传输的高速低功耗光电子集成芯片。公司利用具有自主知识产权和专利的全CMOS高速低功耗光电子芯片设计和制造技术，联合世界领先水平的研究单位和行业内的龙头企业，为快速增长的云计算大数据中心提供在性能、功耗、价格上都有极强竞争力的高性能核心芯片。