深圳招聘

Job Description:
1. This position is for a digital/ASIC design engineer to build next-generation analog/digital
mixed SoC chips.
2. Handling every aspect in ASIC design flow including: architecture, RTL coding,
Verification, Synthesis, DFT, STA and P&R
3. Participate into the chip debug and validation.

Job Requirement:
1. BSEE with minimum 3-year of working experience or MSEE with minimum 1-year of
working experience for starting position
2. MSEE with minimum 3-year of working experience for senior position.
3. Excellent knowledge for ASIC design, such as MOS transistor, arithmetic structure
(addition, multiplication), timing analysis, design for test, meta-stability and etc.
4. Need fundamental understanding for digital signal processing, such as FIR/IIR filter
structure, error correction, decimation and etc.
5. Usage experience (not all of them required) of industry-standard EDA tools, such as
VCS/NC, Design Compiler, PrimeTime, Formality/Conformal and Tetramax/DFT compiler.
6. Experience in bus design(I2C, AHB or AIX), datapath design(Filter, correlation or Cordic)
and logic control (PCS or MAC) will be a plus.
7. Experience in metrics driven verification methodology(systemverilog/UVM based) will
be a plus.
8. Experience in every aspect of ASIC design will be a great plus.

Location: Shanghai

光梓信息科技（上海）有限公司是我国高速光电集成芯片领域内的领军企业之一。公司总部位于上海浦东新区张江高科园区内，由国家领军创新创业团队在国内外***风险投资的支持下创建。光梓科技致力于研发和产业化应用于数据中心、智能传感、5G数据传输的高速低功耗光电子集成芯片。公司利用具有自主知识产权和专利的全CMOS高速低功耗光电子芯片设计和制造技术，联合世界领先水平的研究单位和行业内的龙头企业，为快速增长的云计算大数据中心提供在性能、功耗、价格上都有极强竞争力的高性能核心芯片。