深圳招聘

Job Description:

1. This position is for a digital-ASIC verification engineer to build next-generation analog/mixedsignal SoC chipsets.
2. Responsible for all aspects of UVM (Universal Verification Methodology), from start to finish.
Good knowledge of communication protocols and associated verification IPs (VIPs). Extensive experience
with assertions, cover properties, constrained random testing.
3. Work with other digital designers to verify many aspects of ASIC design flow including:
architecture, RTL coding/Verification, Synthesis, DFT, STA and P&R (for backend designer).
4. Participate in chip debug, validation, and marketing specifications.

Job Requirement:

1. BSEE with minimum 3-year experience or MSEE with minimum 1-year experience of digital
experience.
2. REQUIRED: Experience in metrics-driven verification methodology (System-Verilog/UVM based).
3. Excellent knowledge of ASIC design, such as arithmetic structure (addition, multiplication,
interation), timing analysis, DFT, meta-stability, etc.
4. Fundamental understanding of digital signal processing, such as FIR/IIR filter structure and
decimation.
5. Desired usage experience of mainsteam industry-standard EDA tools, such as VCS/NC, Design
Compiler, PrimeTime, Formality/ Conformal and Tetramax/DFT compiler.
6. Experience in other vertical aspects of ASIC design (front-end and back-end) will be a great plus.
7. Experience in perl/python/tcl scripts is a plus.

Location: Shanghai

光梓信息科技（上海）有限公司是我国高速光电集成芯片领域内的领军企业之一。公司总部位于上海浦东新区张江高科园区内，由国家领军创新创业团队在国内外***风险投资的支持下创建。光梓科技致力于研发和产业化应用于数据中心、智能传感、5G数据传输的高速低功耗光电子集成芯片。公司利用具有自主知识产权和专利的全CMOS高速低功耗光电子芯片设计和制造技术，联合世界领先水平的研究单位和行业内的龙头企业，为快速增长的云计算大数据中心提供在性能、功耗、价格上都有极强竞争力的高性能核心芯片。