深圳招聘

岗位职责：
1 .Perform full cycle of IP development responsibilities, from circuit simulation, FPGA verification to chip validation.
2. communication IP/IC design, implementation and verification

任职要求：
1. Highly efficient in Verilog RTL coding
2. Hands-on experience on ASIC/FPGA design, verification flows, methodologies, network protocol Validation
3. Good understanding of modulator/demodulator design related techniques is a plus
4. Hands-on experience on Ethernet MAC/Switch/Network processing accelerator or 802.11 MAC ASIC/FPGA implementation and verification is a plus
5. 5+ years of solid experience in digital front end design is required, with a proven track record of delivering successful ASICs
6. Good document skills in english
7. Expertise in verification methodology such as systemVerilog/UVM is a plus and highly desired
8. Bachelor's or master's degree in semiconductor, electronic engineering or relevant speciality

工作地址：
深圳市南山区创业路怡海广场东座1706室

深圳鸿年科技有限公司是一家集研发、生产、销售为一体的高科技企业，以电子产品、通讯设备、电子元器件以及周边设备的技术开发与销售、电子数码产品、软件开发、网站设计开发、货物及技术的进出口业务的生产商。