深圳招聘

Responsible for understanding the expected functionality of designs and developing corresponding verification plans.
Designing and developing components of our verification environment using UVM, System Verilog, Verilog, and SATA/PCIe third party VIP's to verify complex SOC's until the functionality coverage are met. In-depth knowledge in SoC architecture, CPU's, AXI Bus Protocol, Peripherals (UART, SPI) and multi-domain clocking. Interacting with different teams in order to observe the functionality of designs flow. We are looking for a Highly motivated engineer to join our team.

We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, We go all in with you. Focused and determined, we unite behind your goals as our own. We leverage our unrivaled portfolio of infrastructure technology to identify the best solution for your unique needs. And we sit shoulder-to-shoulder with your teams to build it. Agile in our thinking, and our partnerships, we look for unexpected connections that deliver a competitive edge and reveal new opportunities. At Marvell, we’re driven by the belief that how we do things matters just as much as what we do. Because, with a foundation built on partnership, anything is possible.

Website: **********************