深圳招聘

Description - External

- Work closely with design team to review design spec and define detailed verification plan.

- Develop UVM testbench environment and tests for the designs.

- Develop functional coverage

- Run RTL and Gate-Level functional verification regressions, debug failures, analyze and improve functional and code coverage.

- Develop and improve verification flow and methodology.

Qualifications - External

- Bachelors or Masters in Electrical, Computer, or Computer Science

- Graduation with high GPA is a plus

- Knowledge of ASIC design and verification flow including RTL design, simulation, synthesis, test bench development, etc.

- Knowledge of System Verilog

- Knowledge of UNIX environment, Perl, Shell scripting

- Knowledge of verification methodology such as UVM/OVM/VMM is a plus

- Good written and oral communication skills in English.

We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, We go all in with you. Focused and determined, we unite behind your goals as our own. We leverage our unrivaled portfolio of infrastructure technology to identify the best solution for your unique needs. And we sit shoulder-to-shoulder with your teams to build it. Agile in our thinking, and our partnerships, we look for unexpected connections that deliver a competitive edge and reveal new opportunities. At Marvell, we’re driven by the belief that how we do things matters just as much as what we do. Because, with a foundation built on partnership, anything is possible.

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