深圳招聘

Candidates will be involved in the whole ASIC design flow from RTL coding through P&R support, which includes logic design, DFT planning and implementation, logic synthesis, power optimization, static timing analysis and sign-off. Candidates will also work closely with analog design teams on IP integration, with P&R engineers on chip floor planning and timing optimization, and with product/test engineers on ATE tests.

Job Description - Duties & Responsibilities: Work closely with frontend and backend design teams, as well as test engineers. Participate in logic design for some timing critical blocks in SOHO switch/PHY chips and ASICs. Perform logic synthesis, floor planning, timing analysis and timing signoff for chip tape out. Work on DFT designs including MBIST, EDT, OCC, JTAG. Run Mentor and Synopsys tools to create and verify ATPG patterns. Work with test engineers to build up and debug test programs.

Required Education, Knowledge, Skills & Abilities:

· MSEE degree

· 0~2 years of hand-on experience in digital design, running EDA tools of simulation, synthesis, timing analysis and formal verification

· Solid knowledge and background in ASIC development

Good communication skills

We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, We go all in with you. Focused and determined, we unite behind your goals as our own. We leverage our unrivaled portfolio of infrastructure technology to identify the best solution for your unique needs. And we sit shoulder-to-shoulder with your teams to build it. Agile in our thinking, and our partnerships, we look for unexpected connections that deliver a competitive edge and reveal new opportunities. At Marvell, we’re driven by the belief that how we do things matters just as much as what we do. Because, with a foundation built on partnership, anything is possible.

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