数字后端工程师-Team Leader
西安紫光国芯半导体有限公司
- 公司规模:150-500人
- 公司性质:上市公司
- 公司行业:电子技术/半导体/集成电路
职位信息
- 发布日期:2017-06-09
- 工作地点:西安
- 招聘人数:1人
- 工作经验:5-7年经验
- 学历要求:本科
- 语言要求:英语 精通 普通话
- 职位月薪:1.5-2万/月
- 职位类别:电子技术研发工程师 半导体技术
职位描述
职位描述:
Responsibilities:
1. Responsible for technical management for team and leading team to finish BE tasks.
2. Work as technical expert to support technical team.
3. Responsible for developing digital designs with emphasis on backend, including Floor-plan, power planning, Place, CTS and Route.
4. Work with Front-end designers to optimize timing/area/power of the design implementation and perform static timing analysis
5. Optimization and Verification of layout for tape-out (including RC extraction, ECO, DRC, LVS).
6. Power IR drop analysis and optimization, area and parasitic layout optimization, chip size optimization.
7. Static Timing analysis (Prime Time) and setup/hold fix.
8. Formal Verification for equivalence checking (Formality).
9. Generation of fill structures according to technology requirements.
Requirements:
1. 1-3 years experience for technical team leadership.
2. About 5 years experience in backend design flow (APR) with proven SOC tape-out experience.
3. Experienced in Synopsys/Cadence automatically physical implementation tools and flows (IC-Compiler/ Astro / SOC-Encounter/ Milky-way/ Star-RCX) is a plus.
4. Experience with one or more scripting languages (Perl, TCL, or Shell) to make reusable automatically flow is a plus.
5. Experience and knowledge about FE design (RTL code, flow) and verification is a plus.
6. Good communication in teamwork spirit.
7. Good analytical and debugging skills.
8. Good command of English.
举报
分享
Responsibilities:
1. Responsible for technical management for team and leading team to finish BE tasks.
2. Work as technical expert to support technical team.
3. Responsible for developing digital designs with emphasis on backend, including Floor-plan, power planning, Place, CTS and Route.
4. Work with Front-end designers to optimize timing/area/power of the design implementation and perform static timing analysis
5. Optimization and Verification of layout for tape-out (including RC extraction, ECO, DRC, LVS).
6. Power IR drop analysis and optimization, area and parasitic layout optimization, chip size optimization.
7. Static Timing analysis (Prime Time) and setup/hold fix.
8. Formal Verification for equivalence checking (Formality).
9. Generation of fill structures according to technology requirements.
Requirements:
1. 1-3 years experience for technical team leadership.
2. About 5 years experience in backend design flow (APR) with proven SOC tape-out experience.
3. Experienced in Synopsys/Cadence automatically physical implementation tools and flows (IC-Compiler/ Astro / SOC-Encounter/ Milky-way/ Star-RCX) is a plus.
4. Experience with one or more scripting languages (Perl, TCL, or Shell) to make reusable automatically flow is a plus.
5. Experience and knowledge about FE design (RTL code, flow) and verification is a plus.
6. Good communication in teamwork spirit.
7. Good analytical and debugging skills.
8. Good command of English.
职能类别: 电子技术研发工程师 半导体技术
公司介绍
西安紫光国芯前身为全球知名的存储器公司-奇梦达科技在西安的研发中心。公司被紫光集团收购后,更名为西安紫光国芯半导体有限公司。
公司核心业务是存储器设计开发,自有品牌存储器产品量产销售,以及专用集成电路设计开发服务。公司拥有丰富的高端存储器设计开发和量产经验,以及完善严谨的产品开发流程管理、质量管理体系。存储器芯片和模组产品持续量产,并销售到国内及欧洲等地。公司拥有大规模的ASIC设计开发团队,使用全球先进开发工艺,具备从设计规格到芯片量产完整流程的开发能力。
西安紫光国芯立足西安,放眼全球,已有16年的发展历史。公司提供先进的设计开发环境,良好的企业文化以及人文关怀,优厚的薪酬待遇,完善的休假体系,全面的社会及商业保险。诚邀有志IC事业的人才加盟共同发展。
公司核心业务是存储器设计开发,自有品牌存储器产品量产销售,以及专用集成电路设计开发服务。公司拥有丰富的高端存储器设计开发和量产经验,以及完善严谨的产品开发流程管理、质量管理体系。存储器芯片和模组产品持续量产,并销售到国内及欧洲等地。公司拥有大规模的ASIC设计开发团队,使用全球先进开发工艺,具备从设计规格到芯片量产完整流程的开发能力。
西安紫光国芯立足西安,放眼全球,已有16年的发展历史。公司提供先进的设计开发环境,良好的企业文化以及人文关怀,优厚的薪酬待遇,完善的休假体系,全面的社会及商业保险。诚邀有志IC事业的人才加盟共同发展。
联系方式
- Email:hr-xian@scsemicon.com
- 公司地址:广东省深圳市南山区大冲商务中心A座2402