深圳招聘

职位描述：
Job Description
-Participate in high speed SERDES PHY design, such as PCIE, USB and SATA.
-Will be involved in the whole ASIC design flow from RTL coding through P&R support, which includes logic design, DFT planning and implementation, logic synthesis, power optimization, static timing analysis and sign-off.
-Will also work closely with analog design teams on IP integration, with P&R engineers on chip floor planning and timing optimization, and with product/test engineers on ATE tests. Work closely with frontend and backend design teams, as well as test engineers.

Job Requirement
-BS or MS in EE/CS
-Excellent knowledge of RTL design and verification.
-Hands-on experience with Verilog, C/C++, Perl, Tcl.
-Experience in PCIE,USB and SATA is a plus. 举报 分享

We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, We go all in with you. Focused and determined, we unite behind your goals as our own. We leverage our unrivaled portfolio of infrastructure technology to identify the best solution for your unique needs. And we sit shoulder-to-shoulder with your teams to build it. Agile in our thinking, and our partnerships, we look for unexpected connections that deliver a competitive edge and reveal new opportunities. At Marvell, we’re driven by the belief that how we do things matters just as much as what we do. Because, with a foundation built on partnership, anything is possible.

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