Sr. GPU DFx DV Engineer
超威半导体（中国）有限公司
- 公司规模：1000-5000人
- 公司性质：外资(欧美)
- 公司行业：电子技术/半导体/集成电路
职位信息
- 发布日期：2016-11-13
- 工作地点：北京
- 招聘人数：1人
- 工作经验：2年经验
- 学历要求：本科
- 语言要求：英语 熟练
- 职位类别：IC验证工程师 半导体技术
职位描述
职位描述：
Job description:
AMD Beijing GPU SOC team is looking for DV engineer that will work on cutting edge GPU projects, to cover the SOC level DFT/DFD logic verification jobs in both pre and post-silicon phases.
Responsibility:
1. SoC DV testbench and infrastructure development and maintenance
2. Create and execute SoC DFT/DFD testplan for logic including SCAN, MBIST, high speed I/O, Debug Bus/Debug Widget, Boundary SCAN etc.
3. Implement directed and random testcase in C++/SV, as well as checkers and assertions
4. Doing coverage analysis and bug cleanup in regression
5. Participate in ATE bring-up, and deliver/debug the DFT patterns that will work on ATE
Requirement:
- MS with 3+ or BS with 5+ years experience in ASIC/SoC design verification
- Knowledge and hand-on experience of complex SoC DV flow from plan to coverage
- Strong C++/SV/Verilog development experience, familiar with scripting languages like Perl, Makefile, ...
- Strong problem solving and communication skills
- Knowledge on DFT/DFD technology such as JTAG, SCAN, MBIST, SerDes loopback is preferred
- Good knowledge on verification methodologies like UVM is a big plus
- Experience in power-aware verification is an asset
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Job description:
AMD Beijing GPU SOC team is looking for DV engineer that will work on cutting edge GPU projects, to cover the SOC level DFT/DFD logic verification jobs in both pre and post-silicon phases.
Responsibility:
1. SoC DV testbench and infrastructure development and maintenance
2. Create and execute SoC DFT/DFD testplan for logic including SCAN, MBIST, high speed I/O, Debug Bus/Debug Widget, Boundary SCAN etc.
3. Implement directed and random testcase in C++/SV, as well as checkers and assertions
4. Doing coverage analysis and bug cleanup in regression
5. Participate in ATE bring-up, and deliver/debug the DFT patterns that will work on ATE
Requirement:
- MS with 3+ or BS with 5+ years experience in ASIC/SoC design verification
- Knowledge and hand-on experience of complex SoC DV flow from plan to coverage
- Strong C++/SV/Verilog development experience, familiar with scripting languages like Perl, Makefile, ...
- Strong problem solving and communication skills
- Knowledge on DFT/DFD technology such as JTAG, SCAN, MBIST, SerDes loopback is preferred
- Good knowledge on verification methodologies like UVM is a big plus
- Experience in power-aware verification is an asset
职能类别： IC验证工程师 半导体技术
关键字： GPU SOC DFx verification
公司介绍
AMD公司成立于1969年，总部位于美国加利福尼亚州桑尼维尔。AMD（NYSE: AMD）是一家创新的科技公司，致力于与客户及合作伙伴紧密合作，开发下一代面向商用、家用和游戏领域的计算和图形处理解决方案。AMD的业务遍布全球，拥有约为12000名员工。
联系方式
- Email：bella.yu@amd.com
- 公司地址：上海-浦东新区 张江 环科路669号凯瑞大厦