苏州招聘

Responsibilities:

- Micro-architecture definition/writing IC design spec.
- RTL coding for logic modules.
- Simulation/Verification of functionalities at both module level and top level.
- Do module level synthesis / timing analysis
- Writing complete design/verification reports
- Silicon debug of the related module functionalities
- Writing test patterns for production tests




QUALIFICATION:
- BSEE with minimum 5-year or MSEE with minimum 3-year experience of digital design experience
- Experience on SERDES is preferred.
- Relevant experience in high-speed digital design (Semi-flow: customer layout + ASIC flow) is must
- Relevant experience in Cadence ICMS/ICFB design environment is must
- Solid knowledge of digital design building blocks (eg. Data-path, Synchronizer, FIFO...)
- Strong skills of Verilog RTL coding and verification and debug.
- Hands on experience in EDA tools such as Cadence NC-Sim, Synopsys DC, PT, etc.
- Relevant experience in DDR interface design is a plus
- Self-motivated and team player




Email:amychen.vision@gmail.com

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