苏州招聘

This position will be responsible for IC full-custom analog layout, verification of the layout (DRC/ERC/LVS/), RC extraction for post simulation.

Description:
1. Full custome analog layout/verification and RC extraction.
2. Perform block level layout. Conduct physical verification (DRC and LVS using Cadence tools).
3. Team work with analog designers, optimize layout.

Qualifications:
1. Bachelor or above degree with 3 years experiences in CMOS IC full-custom layout.
2. Experiences in Mixed signal/analog/high speed layout.
3. Familliar with layout skills and knowledge is must.
4. Good teamwork/communication/positive is must.
5. Familiar with Cadence IC layout and verification tools
6. Having massive IP block experience
7. Familiar with 0.18/0.13/0.09/0.065/0.04 um CMOS process and design rule is a plus.
8. Familiar with ESD/Latch up/antenna and related layout solutions is a plus.
9. Familiar with rule deck is a plus.

灿芯半导体（上海）有限公司成立于2008年7月是中国领先的纯设计代工服务公司，致力于为国内外集成电路厂商提供成套的解决方案。公司具备领先的设计能力，应用已被证明先进的设计流程和方法向客户提供可靠的、低成本的设计服务方案。灿芯的商业模式有别于传统复杂的ASIC芯片设计，它向客户提供的是一种简易、低成本和低风险的ASIC芯片发展和制造方法，已具备覆盖多家晶圆代工厂、封装测试厂及世界一流集成电路厂商的强大合作网络。基于迅猛发展的中国通讯、消费品及计算机市场，灿芯半导体正积极创建可喜成绩、迈进全新里程。

我们的事业前途极富竞争力，并提供良好的工作环境、优厚的福利待遇和广阔的个人职业发展空间。因业务发展需要，我们诚邀微电子、半导体及电子类相关专业人才加盟。

敬请递交详尽个人简历,对符合条件的候选人，公司会尽快安排面试，择优录用。

Brite Semiconductor was founded in 2008 in Shanghai's Zhangjiang Hi-tech district, and is a fast growing SoC and ASIC Design Company aimed at assembling the most optimum IP, foundry, test and packaging technologies to create custom silicon solutions for its customers. Brite is committed to delivering electronics solutions with leading edge North American technology, competitive pricing, uncompromising quality and a customer-centric approach to meet all of a customer's ASIC needs.
 
Brite utilizes the Open Model to provide flexible, direct, and cost effective designs that reduce a chip's time to market. Focused on the customer's needs, Brite's comprehensive customer support supplements turnkey spec-parts solutions, third party manufacturing service, product OEM solutions, and all other design service solutions. Brite's unique MAX technology lowers costs and maximizes yields for advanced 40/45 nm designs. With a proven track record of first time silicon success and the experience of over 200 tapeouts, Brite ensures minimum risk in both frontend and backend physical design, as well as test engineering, packaging and assembly, wafer fabrication, and production support to be our customers' ideal all inclusive ASIC partner