ASIC 数字前端 设计 验证 后端岗位 猎头
上海芯相会企业管理咨询有限公司
- 公司规模：50-150人
- 公司性质：民营公司
- 公司行业：电子技术/半导体/集成电路 互联网/电子商务
职位信息
- 发布日期：2013-10-15
- 工作地点：苏州
- 招聘人数：5
- 职位类别：集成电路IC设计/应用工程师 IC验证工程师
职位描述
3个IC职位，分别是两家公司的，大家加油。简历发HR@hi-talent.net
urgent position to be fulfilled is a ASIC design verification engineer. It needs experiences in CPU design. The JD is as below.
(Sr.) ASIC Design Verification Engineer
Position Description:
As part of the IP design team, the candidate will be responsible for the pre-silicon verification of in-house designed micro-processor which is a built-in component for next generation video codec IP, including:
· Build up and maintain verification environment, including development of testbench and test generators for block-level and full-chip level simulation;
· Develop and execute functional verification test plans, include writing tests, developing behavioral checkers and coverage/code monitors; Analyze coverage gaps and devise strategies to fill coverage holes;
· Work with designers to debug failing tests and resolve bugs;
· Help develop and maintain flows/scripts/tools for front-end design/verification;
Qualification:
· BS with 5+ years or MS with 2+ years experiences in electronic engineering/micro-electronics;
· Self-motivated team player, with strong problem resolving skills;
· Proficient and experienced in high-level verification methodology (VMM/UVM/OVM), Verilog-HDL, and hardware verification language (SystemC/SystemVerilog);
· Familiar with video coding standard, and/or computer architecture/micro-architecture;
· Hands-on experienced in CPU verification, including test plan and test bench development, test case development and test coverage assessment would be a great plus;
· Experiences in assembly programming, and using scripting languages (Perl/Tcl/Bash/Csh) for flow automation;
· Familiar with front-end ASIC design flow;
Position: Sr. ASIC Engineer
1. This candidate should have mobile/high speed interface background and should be interesting in R&D on Video related technologies.
2. IC/IP background. Be interesting in developing and improving New IP.
3. Integration experience, be able to own testchip tapeout.
4. With at least 3-years IP/Product R&D experience.
Job Description
- RTL coding, new logic design, simulation, synthesis.
- Work closely with algorithm engineer to develop/debug new IP/product. Supports FPGA engineer debugging issues on FPGA system.
- Work closely with system/SW engineer to verificate/validate new IP/product on FPGA/System platform.
- Deliver design/verification/application documents.
Qualification and Experience
- Very familiar with the Verilog HDL language;
- Create the RTL architecture for the algorithm;
- Very familiar with C and C++;
- Familiar with FPGA tool, ModelSim, and Synplify.
- Familiar with the flow of the IC design.
Requirements:
- Bachelor/Master degree in electronic/computer engineering
- Demonstrated abilities in working independently
- Strong communication skills
Position: ASIC Engineer of SOC and Video system
Requirements
1. BS or above in microelectronics, electrical engineering or equivalence
2. 3~5 year experience of ASIC EDA tool and front-end design/coding. Video chip experience is preferred.
3. Must have one of following EDA tool experience
a) STA, low power, DFT, synthesis
4. Must have one of following design/coding experience, video related is preferred
a) IP level micro-architecture definition, RTL design, co-work with verification owner
5. Nice to have experience of chip level clock/reset structure definition, low power partition definition
6. Good team work and communication skill (both in Chinese and English).
Responsibility
The candidate will be working on one of following items
1. SOC architecture definition and coordination including clock/reset structure definition, low power partition definition, etc.
2. Full chip timing closure, work closely with backend for tape out sign off
3. Define UPF/CPF, verify low power structure base on RTL or NETLIST level
4. Understand DFT/synthesis flow, provide necessary support
5. Video or processor related IP level micro-architecture definition, RTL design, co-work with verification owner
简历发HR@hi-talent.net
数字集成电路前端设计工程师Digital IC Frontend Design Engineer
Description:
1. Design and develop high-speed and low power digital circuits for the digital signal processing core of the different product lines including audio codec, ADC, PLL
2. Write RTL code for high-speed and multi-clock domain designs.
3. Perform functional verification of designs on block and chip level.
4. Perform synthesis and pre-layout timing closure.
5. Perform the clock domain crossing analysis for the different products lines.
6. Generate the Timing .lib and ATPG package for the different product lines.
7. Provide design documentation, information and support to customer application engineers and customers.
Qualifications:
1. MSEE with 2+ years.
2. Able to write RTL, run simulation, synthesis and timing closure, generate the ATPG package.
3. Understanding the basic mixed-signal circuit including ADC, PLL, and audio codec.
4. Able to perform functional and timing verification for circuit and logic design, know the SVA verification methodology and function coverage.
5. Understanding C and Perl programming.
6. Have a fluent oral and good writing English skill.
数字集成电路前端验证工程师 Digital IC Frontend Verification Engineer
Description:
l Develop and execute verification plan
l Develop and maintain verification environment
l Define and implement functional/code coverage plan
l Functional/code coverage analysis
l Run simulation for module and chip level, report and debug together with designer
l Develop/maintain/enhance environment (TB/tools/scripts/flow)
Requirement:
l MSEE with 2+ years.
l Proficient and experienced in SVA verification methodology
l Experienced with hardware verification language (Vera, Systems, SystemVerilog)
l Proficient with Verilog HDL
l Proficient with at least one scripting languages, e.g. Csh, Bash, Perl, Tcl
l Familiar with ASIC design flow
数字集成电路后端设计工程师 Digital IC Backend Design Engineer
Job Description:
· Digital layout design for blocks and chips;
· RTL synthesis and timing analysis;
· Documentation of design procedures;
· Work toward improving efficiency in design procedures and methodologies;
· Communicate effectively with other team members.
Requirements:
· Knowledge of IC design/EDA tools, technical documentation, utilities;
· Knowledge of Shell/Perl/Python script language programming skill in Unix/Linux environment;
· Has strong desires to learn and explore new technologies and demonstrates good analysis and problem-solving skills;
· Bachelor degree in EE/CS;
· Good English skills to work in an English language environment.
数字集成电路前端设计高级工程师 Digital IC Frontend Design Engineer（Senior）
Description:
l Design and develop high-speed and low power digital circuits for the digital signal processing core of the different product lines including audio codec, ADC, PLL
l Write RTL code for high-speed and multi-clock domain designs.
l Perform functional verification of designs on block and chip level.
l Perform synthesis and pre-layout timing closure.
l Perform the clock domain crossing analysis for the different products lines.
l Generate the Timing .lib and ATPG package for the different product lines.
l Provide design documentation, information and support to customer application engineers and customers.
Qualifications:
l MSEE with 2+ years.
l Able to write RTL, run simulation, synthesis and timing closure, generate the ATPG package.
l Understanding the basic mixed-signal circuit including ADC, PLL, and audio codec.
l Able to perform functional and timing verification for circuit and logic design, know the SVA verification methodology and function coverage.
l Understanding C and Perl programming.
l Have a fluent oral and good writing English skill.
数字集成电路前端设计工程师 Digital IC Frontend Design Engineer
Description:
l Design and develop high-speed and low power digital circuits for the digital signal processing core of the different product lines including audio codec, ADC, PLL
l Write RTL code for high-speed and multi-clock domain designs.
l Perform functional verification of designs on block and chip level.
l Perform synthesis and pre-layout timing closure.
l Perform the clock domain crossing analysis for the different products lines.
l Generate the Timing .lib and ATPG package for the different product lines.
l Provide design documentation, information and support to customer application engineers and customers.
Qualifications:
l MSEE with 2+ years.
l Able to write RTL, run simulation, synthesis and timing closure, generate the ATPG package.
l Understanding the basic mixed-signal circuit including ADC, PLL, and audio codec.
l Able to perform functional and timing verification for circuit and logic design, know the SVA verification methodology and function coverage.
l Understanding C and Perl programming.
l Have a fluent oral and good writing English skill.
数字集成电路后端设计工程师 Digital IC Backend Design Engineer
Job Description:
· Digital layout design for blocks and chips;
· RTL synthesis and timing analysis;
· Documentation of design procedures;
· Work toward improving efficiency in design procedures and methodologies;
· Communicate effectively with other team members.
Requirements:
· Knowledge of IC design/EDA tools, technical documentation, utilities;
· Knowledge of Shell/Perl/Python script language programming skill in Unix/Linux environment;
· Has strong desires to learn and explore new technologies and demonstrates good analysis and problem-solving skills;
· Bachelor degree in EE/CS;
· Good English skills to work in an English language environment.
实际工作地点：苏州
贵司有招聘需求的，欢迎和我联系；
如果你和你朋友有需要看工作机会的，发简历给我Jane-Jin@Hi-Talent.net
urgent position to be fulfilled is a ASIC design verification engineer. It needs experiences in CPU design. The JD is as below.
(Sr.) ASIC Design Verification Engineer
Position Description:
As part of the IP design team, the candidate will be responsible for the pre-silicon verification of in-house designed micro-processor which is a built-in component for next generation video codec IP, including:
· Build up and maintain verification environment, including development of testbench and test generators for block-level and full-chip level simulation;
· Develop and execute functional verification test plans, include writing tests, developing behavioral checkers and coverage/code monitors; Analyze coverage gaps and devise strategies to fill coverage holes;
· Work with designers to debug failing tests and resolve bugs;
· Help develop and maintain flows/scripts/tools for front-end design/verification;
Qualification:
· BS with 5+ years or MS with 2+ years experiences in electronic engineering/micro-electronics;
· Self-motivated team player, with strong problem resolving skills;
· Proficient and experienced in high-level verification methodology (VMM/UVM/OVM), Verilog-HDL, and hardware verification language (SystemC/SystemVerilog);
· Familiar with video coding standard, and/or computer architecture/micro-architecture;
· Hands-on experienced in CPU verification, including test plan and test bench development, test case development and test coverage assessment would be a great plus;
· Experiences in assembly programming, and using scripting languages (Perl/Tcl/Bash/Csh) for flow automation;
· Familiar with front-end ASIC design flow;
Position: Sr. ASIC Engineer
1. This candidate should have mobile/high speed interface background and should be interesting in R&D on Video related technologies.
2. IC/IP background. Be interesting in developing and improving New IP.
3. Integration experience, be able to own testchip tapeout.
4. With at least 3-years IP/Product R&D experience.
Job Description
- RTL coding, new logic design, simulation, synthesis.
- Work closely with algorithm engineer to develop/debug new IP/product. Supports FPGA engineer debugging issues on FPGA system.
- Work closely with system/SW engineer to verificate/validate new IP/product on FPGA/System platform.
- Deliver design/verification/application documents.
Qualification and Experience
- Very familiar with the Verilog HDL language;
- Create the RTL architecture for the algorithm;
- Very familiar with C and C++;
- Familiar with FPGA tool, ModelSim, and Synplify.
- Familiar with the flow of the IC design.
Requirements:
- Bachelor/Master degree in electronic/computer engineering
- Demonstrated abilities in working independently
- Strong communication skills
Position: ASIC Engineer of SOC and Video system
Requirements
1. BS or above in microelectronics, electrical engineering or equivalence
2. 3~5 year experience of ASIC EDA tool and front-end design/coding. Video chip experience is preferred.
3. Must have one of following EDA tool experience
a) STA, low power, DFT, synthesis
4. Must have one of following design/coding experience, video related is preferred
a) IP level micro-architecture definition, RTL design, co-work with verification owner
5. Nice to have experience of chip level clock/reset structure definition, low power partition definition
6. Good team work and communication skill (both in Chinese and English).
Responsibility
The candidate will be working on one of following items
1. SOC architecture definition and coordination including clock/reset structure definition, low power partition definition, etc.
2. Full chip timing closure, work closely with backend for tape out sign off
3. Define UPF/CPF, verify low power structure base on RTL or NETLIST level
4. Understand DFT/synthesis flow, provide necessary support
5. Video or processor related IP level micro-architecture definition, RTL design, co-work with verification owner
简历发HR@hi-talent.net
数字集成电路前端设计工程师Digital IC Frontend Design Engineer
Description:
1. Design and develop high-speed and low power digital circuits for the digital signal processing core of the different product lines including audio codec, ADC, PLL
2. Write RTL code for high-speed and multi-clock domain designs.
3. Perform functional verification of designs on block and chip level.
4. Perform synthesis and pre-layout timing closure.
5. Perform the clock domain crossing analysis for the different products lines.
6. Generate the Timing .lib and ATPG package for the different product lines.
7. Provide design documentation, information and support to customer application engineers and customers.
Qualifications:
1. MSEE with 2+ years.
2. Able to write RTL, run simulation, synthesis and timing closure, generate the ATPG package.
3. Understanding the basic mixed-signal circuit including ADC, PLL, and audio codec.
4. Able to perform functional and timing verification for circuit and logic design, know the SVA verification methodology and function coverage.
5. Understanding C and Perl programming.
6. Have a fluent oral and good writing English skill.
数字集成电路前端验证工程师 Digital IC Frontend Verification Engineer
Description:
l Develop and execute verification plan
l Develop and maintain verification environment
l Define and implement functional/code coverage plan
l Functional/code coverage analysis
l Run simulation for module and chip level, report and debug together with designer
l Develop/maintain/enhance environment (TB/tools/scripts/flow)
Requirement:
l MSEE with 2+ years.
l Proficient and experienced in SVA verification methodology
l Experienced with hardware verification language (Vera, Systems, SystemVerilog)
l Proficient with Verilog HDL
l Proficient with at least one scripting languages, e.g. Csh, Bash, Perl, Tcl
l Familiar with ASIC design flow
数字集成电路后端设计工程师 Digital IC Backend Design Engineer
Job Description:
· Digital layout design for blocks and chips;
· RTL synthesis and timing analysis;
· Documentation of design procedures;
· Work toward improving efficiency in design procedures and methodologies;
· Communicate effectively with other team members.
Requirements:
· Knowledge of IC design/EDA tools, technical documentation, utilities;
· Knowledge of Shell/Perl/Python script language programming skill in Unix/Linux environment;
· Has strong desires to learn and explore new technologies and demonstrates good analysis and problem-solving skills;
· Bachelor degree in EE/CS;
· Good English skills to work in an English language environment.
数字集成电路前端设计高级工程师 Digital IC Frontend Design Engineer（Senior）
Description:
l Design and develop high-speed and low power digital circuits for the digital signal processing core of the different product lines including audio codec, ADC, PLL
l Write RTL code for high-speed and multi-clock domain designs.
l Perform functional verification of designs on block and chip level.
l Perform synthesis and pre-layout timing closure.
l Perform the clock domain crossing analysis for the different products lines.
l Generate the Timing .lib and ATPG package for the different product lines.
l Provide design documentation, information and support to customer application engineers and customers.
Qualifications:
l MSEE with 2+ years.
l Able to write RTL, run simulation, synthesis and timing closure, generate the ATPG package.
l Understanding the basic mixed-signal circuit including ADC, PLL, and audio codec.
l Able to perform functional and timing verification for circuit and logic design, know the SVA verification methodology and function coverage.
l Understanding C and Perl programming.
l Have a fluent oral and good writing English skill.
数字集成电路前端设计工程师 Digital IC Frontend Design Engineer
Description:
l Design and develop high-speed and low power digital circuits for the digital signal processing core of the different product lines including audio codec, ADC, PLL
l Write RTL code for high-speed and multi-clock domain designs.
l Perform functional verification of designs on block and chip level.
l Perform synthesis and pre-layout timing closure.
l Perform the clock domain crossing analysis for the different products lines.
l Generate the Timing .lib and ATPG package for the different product lines.
l Provide design documentation, information and support to customer application engineers and customers.
Qualifications:
l MSEE with 2+ years.
l Able to write RTL, run simulation, synthesis and timing closure, generate the ATPG package.
l Understanding the basic mixed-signal circuit including ADC, PLL, and audio codec.
l Able to perform functional and timing verification for circuit and logic design, know the SVA verification methodology and function coverage.
l Understanding C and Perl programming.
l Have a fluent oral and good writing English skill.
数字集成电路后端设计工程师 Digital IC Backend Design Engineer
Job Description:
· Digital layout design for blocks and chips;
· RTL synthesis and timing analysis;
· Documentation of design procedures;
· Work toward improving efficiency in design procedures and methodologies;
· Communicate effectively with other team members.
Requirements:
· Knowledge of IC design/EDA tools, technical documentation, utilities;
· Knowledge of Shell/Perl/Python script language programming skill in Unix/Linux environment;
· Has strong desires to learn and explore new technologies and demonstrates good analysis and problem-solving skills;
· Bachelor degree in EE/CS;
· Good English skills to work in an English language environment.
实际工作地点：苏州
贵司有招聘需求的，欢迎和我联系；
如果你和你朋友有需要看工作机会的，发简历给我Jane-Jin@Hi-Talent.net
公司介绍
Principal Consultant & General Manager @ Hi-Talent Consulting Co.,Ltd.
上海芯得企业管理咨询有限公司
上海芯相会企业管理咨询有限公司
上海戴引企业管理咨询有限公司
专注于IC和IT 互联网 金融 高科技领域的猎头公司
上海芯得企业管理咨询有限公司
上海芯相会企业管理咨询有限公司
上海戴引企业管理咨询有限公司
专注于IC和IT 互联网 金融 高科技领域的猎头公司
联系方式
- Email：hr@hi-talent.com
- 公司地址：上班地址：上海