苏州 [切换城市] 苏州招聘苏州质量管理/安全防护招聘苏州故障分析工程师招聘

Sr. Failure Analysis Engineer (当前在招)

超威半导体技术(中国)有限公司

  • 公司性质:外资(欧美)
  • 公司行业:电子技术/半导体/集成电路

职位信息

  • 发布日期:2013-09-09
  • 工作地点:苏州-工业园区
  • 招聘人数:1
  • 工作经验:五年以上
  • 学历要求:本科
  • 语言要求:英语熟练
  • 职位类别:故障分析工程师  

职位描述

Requirement:
1;Bachelor’s degree in Electrical Engineering, or equivalent
2;4-8 years experience in electronic test (ATE, System Level Test, Functional Testing) and debugging digital and analog electronic circuits using laboratory equipment (oscilloscopes, logic analyzers, DMM, Curve tracer)
3;Demonstrated assertive leadership skills
4;Strong communication skills, both verbal and written
5;Effective time management skills, able to manage multiple open cases simultaneously
6;Proficient at problem solving and continuous improvement
7;Advanced working level knowledge of DOS, LINUX, JAVA & Windows, as well as PC systems and graphics processors
8;Knowledge of high-speed digital design, analog design, memory interface, bus (AGP, PCI, PCI-e) interface, ASIC verification, and applications engineering

Desired Skills/Experience:

1;ATE test experience (Scan Diagnostic, BIST, Analog, etc)
2;Understanding of fundamental Quality systems, Pareto analysis, 8D methodology
3;Knowledge or experience in Electronic Design and Test Methodology
4;Knowledge or experience in Platform debug/troubleshooting
5;Knowledge or experience in Surface Mount Technology, Printed Circuit Board Assembly, Advanced Packaging, Semiconductor Wafer Fabrication knowledge or experience
6;Knowledge or experience in Electrical fault isolation, silicon and package level physical failure analysis techniques, including SEM, EDX, TDR, X-Ray, C-SAM, FIB, TIVA, LIVA, Thermal Emission microscopy, Photon Emission Microscopy, IR microscopy, TRE, Laser Scanning microscopy

Job Description:

The Failure Analysis team within the Quality Engineering organization is responsible for analyzing failing ASICs and boards (GPUs/Chipsets) within required time frames, with the use of electrical test methods and physical FA as needed. The role of the Failure Analysis Engineer is to perform failure analysis on failed samples provided by external and internal customers to determine the root cause of the reported failures and work with appropriate technical owners on preventative and corrective actions to address the failures.

Responsibilities:

1;Lead and perform customer returns electrical debug (ATE, SLT, Diagnostics) to determine root cause analysis of failed ASICs and graphics boards/modules to performance standards within required timeframes
2;Document all analysis findings real-time as obtained into online LMS FA database
3;Where applicable, direct physical debug and/or die-level analysis as needed
4;After root cause determination, identify accountable issue owner (Systems Engineering, Product and Test Engineering, Diagnostic Engineering, S/W Engineering, CQE, Board Operations, Logistics, etc) and initiate request for corrective and preventative actions
5;Support internal and external customers to troubleshoot product failures for continuous yield improvement activities
6;If required, participate in customer calls on technical issues related to debug findings
7;Continuous improvement of debug processes and techniques

公司介绍

AMD(NASDAQ: AMD)设计并集成尖端技术,为包括个人电脑、平板电脑、游戏机和云服务器等在内的数千万的智能设备提供强大动力,开启环绕计算的新时代。AMD解决方案让人们随时随地尽享其青睐的设备和应用的全部潜力,不断创造新的可能。
更多详情,敬请访问www.amd.com。

联系方式

  • Email:HR.SZ@amd.com