Digtial IP Design ＆ Verification Engineer Intern
飞思卡尔半导体（中国）有限公司上海分公司
- 公司行业：电子技术/半导体/集成电路
职位信息
- 发布日期：2013-09-09
- 工作地点：苏州
- 招聘人数：若干
- 工作经验：在读学生
- 学历要求：硕士
- 语言要求：英语熟练
- 职位类别：集成电路IC设计/应用工程师
职位描述
Job Description:
Develop and maintain digital IP for various products, from concept to RTL;
?Work on IP level verification;
?Work on IP level synthesis, static timing analysis and formal verification.
?Proactively develop achievable delivery schedules including net list, directed verification or random verification.
Qualification:
Master Degree in Electrical or Computer Engineering.
?Familiar with digital circuit design and analysis.
?Familiar with computer architecture and organization.
?Good RTL coding techniques with Verilog HDL.
?Strong background in C
?Experience on synthesis, timing analysis and formal verification is a plus
?Familiar with SystemVerilog is a plus
?Familiar with UVM is a plus
?Working knowledge of Perl scripting and Makefiles
?Working knowledge of UNIX/Linux operating systems and debugging tools