MTS/Senior Staff Design Architect for 10GE+ IP
超威半导体（中国）有限公司
- 公司规模：1000-5000人
- 公司性质：外资(欧美)
- 公司行业：电子技术/半导体/集成电路
职位信息
- 发布日期：2014-05-06
- 工作地点：上海
- 招聘人数：若干
- 学历要求：本科
- 职位类别：集成电路IC设计/应用工程师 系统架构设计师
职位描述
Position Summary
Job Title: Principle/Senior Staff Design Architect for 10GE+ IP
City/Town: Shanghai
Country: China
- Own IP architecture definition, derive functional and design specifications and analyze feasibility of technical and architectures.
- Discuss with SW architect to generate an optimized HW/SW partition of the system architecture
- Guide the design team to implement design with Verilog to achieve specification goals. Simulate and debug the codes in coding stage.
- Support the Front-End Integration team to deliver qualified netlist. Feedback to Physical Design team to help to close timing and check floorplan.
- Support FW/SW bring-up and debugging
- Working as the overall technical expert of contact on the 10GE area.
Essential Functions:
Architecture, Algorithm, RTL, Performance modeling
Essential Requirements:
- Rich Experience in 10GE+ IP solution, including HW IP and SW stack
- Deep understanding of
? 10GbE+ solutions from the industry leading companies
? basic offload engines used in 10GbE/40GbE, such as
o TCP transmit segmentation offloading
o TCP Large receive offload
o Receive side scaling
? Basic filtering and Classification: Unicast/multicast/broadcast, ACLs
? Advanced filtering and classification: flow based and L3 protocol based
? Data-center bridging, PFC/ETS/DCBX/QCN
? Device virtualization, SR-IOV/VEB/VEPA
? Advanced offload engine
o TCP offload: TOE
o Storage offload: iSCSI HBA/FCoE HBA
o RDMA: RoCE/iWARP
o Security offload: IPSec
? PHY interfaces
- Good English hearing, speaking, reading and writing capabilities
- Good communication skills
- Have mass production tape﹐ut experience
- Should have strong problem solving skills
Position Summary
Job Title: Senior Staff/Staff Design Lead for Wired Connection IP
City/Town: Shanghai
Country: China
- Participate IP and SoC level architecture definition, create IP architectural spec, derive functional and design specifications and analyze feasibility of technical and architectures.
- Implement design with Verilog to achieve specification goals. Simulate and debug the codes in coding stage.
- Define timing constraints and support the FE Integration team to deliver qualified netlist. Feedback to Physical Design team to help to close timing and check floorplan
- Discuss with SW team to generate an optimized HW/SW partition of the functionalities
- Support FW/SW bring-up and debugging
- Working as the technical point of contact in the Wired Connection IP area.
- Maintain design environment, solve flow issues, and develop scripts to improve flow efficiency.
Essential Functions:
Architecture, RTL, Synthesis, STA, Timing Analysis, Constraints
Essential Requirements/Qualifications:
- Proven IP / SoC Design / Integration Experience
- Must have strong background on IP development
Desired:
- Enthusiasm on technical topics
- Major in EE & CS
- Must be proficient in Verilog coding, debugging and modeling
- Deep understanding of below technical aspects would be an asset:
? 10GbE+ solutions from the industry leading companies
? basic offload engines used in 10GbE/40GbE, such as
o TCP transmit segmentation offloading
o TCP Large receive offload
o Receive side scaling
? Basic filtering and Classification: Unicast/multicast/broadcast, ACLs
? Advanced filtering and classification: flow based and L3 protocol based
? Data-center bridging, PFC/ETS/DCBX/QCN
? Device virtualization, SR-IOV/VEB/VEPA
? Advanced offload engine
o TCP offload: TOE
o Storage offload: iSCSI HBA/FCoE HBA
o RDMA: RoCE/iWARP
o Security offload: IPSec
- 10 gigabit+ Ethernet IP design experience would be an asset
- Ethernet HW/SW performance analysis experience would be an asset
- Be familiar with ASIC design flow, such as synthesis, DFT, timing analysis, ECO etc
- Be familiar with shell/perl/tcl programming in linux OS.
- Should have strong problem solving skills
- Good English hearing, speaking, reading and writing capabilities
- Good communication skills
- Have mass production tape﹐ut experience
Job Title: Principle/Senior Staff Design Architect for 10GE+ IP
City/Town: Shanghai
Country: China
- Own IP architecture definition, derive functional and design specifications and analyze feasibility of technical and architectures.
- Discuss with SW architect to generate an optimized HW/SW partition of the system architecture
- Guide the design team to implement design with Verilog to achieve specification goals. Simulate and debug the codes in coding stage.
- Support the Front-End Integration team to deliver qualified netlist. Feedback to Physical Design team to help to close timing and check floorplan.
- Support FW/SW bring-up and debugging
- Working as the overall technical expert of contact on the 10GE area.
Essential Functions:
Architecture, Algorithm, RTL, Performance modeling
Essential Requirements:
- Rich Experience in 10GE+ IP solution, including HW IP and SW stack
- Deep understanding of
? 10GbE+ solutions from the industry leading companies
? basic offload engines used in 10GbE/40GbE, such as
o TCP transmit segmentation offloading
o TCP Large receive offload
o Receive side scaling
? Basic filtering and Classification: Unicast/multicast/broadcast, ACLs
? Advanced filtering and classification: flow based and L3 protocol based
? Data-center bridging, PFC/ETS/DCBX/QCN
? Device virtualization, SR-IOV/VEB/VEPA
? Advanced offload engine
o TCP offload: TOE
o Storage offload: iSCSI HBA/FCoE HBA
o RDMA: RoCE/iWARP
o Security offload: IPSec
? PHY interfaces
- Good English hearing, speaking, reading and writing capabilities
- Good communication skills
- Have mass production tape﹐ut experience
- Should have strong problem solving skills
Position Summary
Job Title: Senior Staff/Staff Design Lead for Wired Connection IP
City/Town: Shanghai
Country: China
- Participate IP and SoC level architecture definition, create IP architectural spec, derive functional and design specifications and analyze feasibility of technical and architectures.
- Implement design with Verilog to achieve specification goals. Simulate and debug the codes in coding stage.
- Define timing constraints and support the FE Integration team to deliver qualified netlist. Feedback to Physical Design team to help to close timing and check floorplan
- Discuss with SW team to generate an optimized HW/SW partition of the functionalities
- Support FW/SW bring-up and debugging
- Working as the technical point of contact in the Wired Connection IP area.
- Maintain design environment, solve flow issues, and develop scripts to improve flow efficiency.
Essential Functions:
Architecture, RTL, Synthesis, STA, Timing Analysis, Constraints
Essential Requirements/Qualifications:
- Proven IP / SoC Design / Integration Experience
- Must have strong background on IP development
Desired:
- Enthusiasm on technical topics
- Major in EE & CS
- Must be proficient in Verilog coding, debugging and modeling
- Deep understanding of below technical aspects would be an asset:
? 10GbE+ solutions from the industry leading companies
? basic offload engines used in 10GbE/40GbE, such as
o TCP transmit segmentation offloading
o TCP Large receive offload
o Receive side scaling
? Basic filtering and Classification: Unicast/multicast/broadcast, ACLs
? Advanced filtering and classification: flow based and L3 protocol based
? Data-center bridging, PFC/ETS/DCBX/QCN
? Device virtualization, SR-IOV/VEB/VEPA
? Advanced offload engine
o TCP offload: TOE
o Storage offload: iSCSI HBA/FCoE HBA
o RDMA: RoCE/iWARP
o Security offload: IPSec
- 10 gigabit+ Ethernet IP design experience would be an asset
- Ethernet HW/SW performance analysis experience would be an asset
- Be familiar with ASIC design flow, such as synthesis, DFT, timing analysis, ECO etc
- Be familiar with shell/perl/tcl programming in linux OS.
- Should have strong problem solving skills
- Good English hearing, speaking, reading and writing capabilities
- Good communication skills
- Have mass production tape﹐ut experience
公司介绍
AMD公司成立于1969年，总部位于美国加利福尼亚州桑尼维尔。AMD（NYSE: AMD）是一家创新的科技公司，致力于与客户及合作伙伴紧密合作，开发下一代面向商用、家用和游戏领域的计算和图形处理解决方案。AMD的业务遍布全球，拥有约为12000名员工。
联系方式
- Email：bella.yu@amd.com
- 公司地址：上海-浦东新区 张江 环科路669号凯瑞大厦