MTS for Graphics Hardware Verification
超威半导体(中国)有限公司
- 公司规模:1000-5000人
- 公司性质:外资(欧美)
- 公司行业:电子技术/半导体/集成电路
职位信息
- 发布日期:2014-05-06
- 工作地点:上海
- 招聘人数:若干
- 学历要求:本科
- 职位类别:IC验证工程师 集成电路IC设计/应用工程师
职位描述
Position Summary
In this key role, the candidate will be responsible for low power implementation and verification of hardware.
Key Relationships
Report To: Manager of SRDC
Essential Functions:
? Development of infrastructure for verification of hardware in GFX IP.
? Develop verification environments for feature verification, and use the automated regression infrastructure setup for IP level and IP on SoC level functional verification.
? Low power design and verification for specific hardware functionality in Front-end.
? Improve the low power IP delivery for variant SoCs
Requirements/Qualifications:
? BS, MS or PhD in Electrical Engineering or Computer Science.
? 6+ years of ASIC verification or low power design experience
? Should have good understanding of Pre-Silicon design process from Architecture, Design, Synthesis and Gate level Implementation till Tapeout release.
? Advanced programming knowledge on Verilog/SystemVerilog, C/C++
? Requires demonstrated technical expertise in the areas of Design Verification and low power design/verification methodology.
? Knowledge on Perforce, OVL, SVA, SV, UVM, script programming etc.
? Should have excellent communication skills (both written and oral) and should be able to participate cross functional engineering teams geographically.
? Demonstrates leadership ability preferred.
Skills/Competencies:
? Good design verification experience
? Good communication
? Strong problem solving skills
? Low power design verification or computer graphics knowledge are plus
Desired:
? Team Lead experience
? Design Verification experience
In this key role, the candidate will be responsible for low power implementation and verification of hardware.
Key Relationships
Report To: Manager of SRDC
Essential Functions:
? Development of infrastructure for verification of hardware in GFX IP.
? Develop verification environments for feature verification, and use the automated regression infrastructure setup for IP level and IP on SoC level functional verification.
? Low power design and verification for specific hardware functionality in Front-end.
? Improve the low power IP delivery for variant SoCs
Requirements/Qualifications:
? BS, MS or PhD in Electrical Engineering or Computer Science.
? 6+ years of ASIC verification or low power design experience
? Should have good understanding of Pre-Silicon design process from Architecture, Design, Synthesis and Gate level Implementation till Tapeout release.
? Advanced programming knowledge on Verilog/SystemVerilog, C/C++
? Requires demonstrated technical expertise in the areas of Design Verification and low power design/verification methodology.
? Knowledge on Perforce, OVL, SVA, SV, UVM, script programming etc.
? Should have excellent communication skills (both written and oral) and should be able to participate cross functional engineering teams geographically.
? Demonstrates leadership ability preferred.
Skills/Competencies:
? Good design verification experience
? Good communication
? Strong problem solving skills
? Low power design verification or computer graphics knowledge are plus
Desired:
? Team Lead experience
? Design Verification experience
公司介绍
AMD公司成立于1969年,总部位于美国加利福尼亚州桑尼维尔。AMD(NYSE: AMD)是一家创新的科技公司,致力于与客户及合作伙伴紧密合作,开发下一代面向商用、家用和游戏领域的计算和图形处理解决方案。AMD的业务遍布全球,拥有约为12000名员工。
联系方式
- Email:bella.yu@amd.com
- 公司地址:上海-浦东新区 张江 环科路669号凯瑞大厦