Design Verification Engineer-SOC
超威半导体(中国)有限公司
- 公司规模:1000-5000人
- 公司性质:外资(欧美)
- 公司行业:电子技术/半导体/集成电路
职位信息
- 发布日期:2021-06-04
- 工作地点:上海-浦东新区
- 招聘人数:若干人
- 工作经验:5-7年经验
- 学历要求:本科
- 职位类别:IC验证工程师
职位描述
What you do at AMD changes everything
At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies-building blocks for gaming, Immersive platforms, and the data center.
Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
SOC Design and Verification Engineer
THE ROLE:
It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash host controller/BCH/doubledatarate interface, PCIE/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
THE PERSON:
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge that facilitates integrative thinking, driving execution of quality and timely result, capability to solve complex, novel and no-recurring problems and decision making on critical technical areas.
RESPONSIBILITIES:
? Work with global SOC design team for large scale ASIC chip verification and emulation implementation.
? Focus on SOC feature verification, emulation model development, FW/SW verification, performance and power analysis etc.
? Responsible for multiple aspects in verification areas and provide technically leadership to the engineering team.
? Accountable for project delivery.
REQUIREMENTS:
? Familiar with Unix/Linux environment and good at scripts
? Understand the architecture of the chip and functional block being designed
? Build C/C++ model for simulation
? Build test bench and monitors for DUT using UVM, SV language
? Compose test plan and validation vectors to ensure functional completeness
? Debug function/performance bugs of graphics chips
Preferred Experience:
? Familiar with emulation Environment (including Zebu and Veloce platform and tools)
? Experience with design for verification (assertion based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.)
? Should be versatile in any one of the high level verification flow such as SV,VMM,VERA,OVM etc as well as knowledge of industry standard tools for verification
? Should have excellent communication skills (both written and oral)
? Strong problem solving skills
? Understanding on Emulation model development and compile flow
? GPU or large SOC verification/validation experiences is a plus
? RTL coding with Verilog/System Verilog and familiar with C/C++ programming
? Use of Mentor's/Synopsys'Veloce/Zebu emulator
EDUCATION:
? Major in EE, CS or related, Master Degree or Bachelor with 6+ years working experiences
LOCATION:
? Shanghai
职能类别:IC验证工程师
公司介绍
联系方式
- Email:bella.yu@amd.com
- 公司地址:上海-浦东新区 张江 环科路669号凯瑞大厦