81489 Sr./MTS Design Verification Engineer
超威半导体(中国)有限公司
- 公司规模:1000-5000人
- 公司性质:外资(欧美)
- 公司行业:电子技术/半导体/集成电路
职位信息
- 发布日期:2020-11-12
- 工作地点:上海-浦东新区
- 招聘人数:若干人
- 工作经验:3-4年经验
- 学历要求:硕士
- 职位类别:算法工程师
职位描述
THE ROLE:
AMD ISP team is looking for a senior/MTS verification engineer responsible for verification work for AMD future products. He/she will be a key technical member in verification team and co-work with different functional teams (Architect, Algorithm, Design, Firmware, etc.) to deliver AMD ISP subsystem designs for APU/GPU. He/She will have the opportunity to work with a smart teammate to develop a chip from end to end and touch industry-advanced design verification flows, methodologies, and knowledge.
THE PERSON:
A quick learner for new technologies. Highly self-motivated. Excellent communication skill (both verbal and written). Key performance skills include decision making, problem solving, teamwork.
KEY RESPONSIBILITIES:
· Understand the architecture and algorithm of the ISP, responsible for verification in ISP delivery for each generation
· Develop UVM test bench on both block level and IP level for test
· Develop C++/SystemC model for simulation and image quality check
· Compose test plan, verification vectors, functional cover groups to ensure functional completeness
· Work with RTL designers and algorithm teams to close all possible issues during implementation
· Participate in new methodology adoption including VC-formal, HLS, UVM-SystemC
· Work on verification tasks on FPGA platforms and emulation platforms
· Work with global teams(Algorithm, design, firmware, software, tuning, SOC, DFT… ) to enable ISP solutions on productions.
PREFERRED EXPERIENCE:
· Familiar with ASIC Frond-End implementation flow and hands-on experiences in ASIC verification for at least 3 years
· Solid knowledge of SystemVerilog and UVM methodology
· Strong c/c++ programming skills is highly preferred
· Good knowledge of Unix/Linux, Makefile and scripts (TCL, Ruby, Perl, Python etc.)
· Experience with Systemic and TLM would be strong advantage
· Experience with PHY, embedded core, low power verification would be strong advantage
· Experience with Image Signal Processing or multi-media IPs is a big plus
· Experience with VC-formal would be a plus
· Strong problem-solving skills, and attention to details
· Good interpersonal skills (verbal and written)
· A self-motivated team player
ACADEMIC CREDENTIALS:
· MS-EE / MS-CE with 3+ years directly related experience.
LOCATION:
· Shanghai, Pudong, Zhangjiang
职能类别:算法工程师
公司介绍
联系方式
- Email:bella.yu@amd.com
- 公司地址:上海-浦东新区 张江 环科路669号凯瑞大厦