DFT engineer
苏州兆芯半导体科技有限公司
- 公司规模：50-150人
- 公司性质：民营公司
- 公司行业：电子技术/半导体/集成电路
职位信息
- 发布日期：2013-01-09
- 工作地点：苏州
- 招聘人数：若干
- 工作经验：三年以上
- 学历要求：本科
- 职位类别：集成电路IC设计/应用工程师
职位描述
Job Description
- Responsible for the development of Ahigh-coverage DFT scheme, DFT methodology and manufacturing test flow
- Responsible for the development ATPG patterns for stuck-at, delay, bridging and iddq faults.
- Responsible for writing test vectors for ATE, verify, and convert them into tester format
- Implement module in RTL using Verilog and assertions.d and backend design team.
Job Requirement
- 3 years of experience in large VLSI physical design implementation and automation and methodology.
- Strong background in DFT, BIST, JTAG/BS and ATPG.
- Extensive hands-on experience with either Mentor DftAdvisor/Fastscan or Synopsys TetraMax
- Memory Design and Synopsys STAR memory system experience is plus
- Responsible for the development of Ahigh-coverage DFT scheme, DFT methodology and manufacturing test flow
- Responsible for the development ATPG patterns for stuck-at, delay, bridging and iddq faults.
- Responsible for writing test vectors for ATE, verify, and convert them into tester format
- Implement module in RTL using Verilog and assertions.d and backend design team.
Job Requirement
- 3 years of experience in large VLSI physical design implementation and automation and methodology.
- Strong background in DFT, BIST, JTAG/BS and ATPG.
- Extensive hands-on experience with either Mentor DftAdvisor/Fastscan or Synopsys TetraMax
- Memory Design and Synopsys STAR memory system experience is plus
公司介绍
苏州兆芯半导体科技有限公司于2012年3月在苏州工业园区创意产业园成立，资金1800万元人民币，从事先进工艺基础IP库研发，为半导体设计公司提供全套基础IP库的解决方案。同时，为集成电路设计公司提供特种基础IP库的定制化及相关设计服务业务。公司将提供高度灵活的用人机制，有竞争力的薪酬待遇，为个人发展提供广阔的空间。我们期待您的加入，携手共进,与公司一起共同成长、共创双赢!