Low Power Design Engineer 79836
超威半导体(中国)有限公司
- 公司规模:1000-5000人
- 公司性质:外资(欧美)
- 公司行业:电子技术/半导体/集成电路
职位信息
- 发布日期:2020-08-22
- 工作地点:上海-浦东新区
- 招聘人数:若干人
- 工作经验:3-4年经验
- 学历要求:本科
- 职位月薪:2-2.5万/月
- 职位类别:集成电路IC设计/应用工程师
职位描述
Low Power Design Engineer
THE ROLE:
Work in Shanghai RPPG group of RTG. We keep improving PPA of every graphic chip and especially focus on their power performance. As the team member, you will take the responsibility to provide accurate power reporting flow, power optimization solution of block design, exploration on power saving feature of EDA tools and so on. You’ll have access to cutting-edge technology/tools/process. Join us if you have much interest in power optimization or you want to develop your competence in a wide range of block design/DV/Synthesize/P&R/….
THE PERSON:
Low power design engineer who has much interest in low power optimization will be involved in many aspects of IC design. Work closely with RTL Design team, design verification team and backend physical design teams across multiple sites. Good communication skill and team spirit. Strong issue debugging capability
KEY RESPONSIBILITIES:
- Work with global Front-End design team, physical design team, methodology team for improving large scale ASIC chips performance/watt performance.
- Defining low power methodology of block design implementation
- Driving Low power optimization cross multi-IP/SOC teams
- Develop power simulation flow for power reporting and debug the abnormal data
- Termly deliver, check and analyze power report
PREFERRED EXPERIENCE:
- the architecture of the graphics IP or functional block preferred
- Wide knowledge of entire IC process from Design specification, defining architecture, micro-architecture, RTL design and functional verification, synthesis, Physical Design, Timing closure, Tape-out, and post-Si debug
- Hands-on experience on one of the following areas: driving Low power design / defining low power methodology / Block or Chip level RTL Design / block or Chip level design verification.
- Design implementation (from synthesis to P&R) experience preferred.
- Expertise in the knowledge of how to get power data desired
- Having proficiency in flow development and scripting (PERL, TCL, PYTHON, SHELL) is a strong plus.
ACADEMIC CREDENTIALS:
- Master with 3 years or Bachelor with 5 years working experience in ASIC area
LOCATION:
Shanghai
职能类别:集成电路IC设计/应用工程师
公司介绍
联系方式
- Email:bella.yu@amd.com
- 公司地址:上海-浦东新区 张江 环科路669号凯瑞大厦