PCIE Architect
超威半导体(中国)有限公司
- 公司规模:1000-5000人
- 公司性质:外资(欧美)
- 公司行业:电子技术/半导体/集成电路
职位信息
- 发布日期:2019-11-28
- 工作地点:北京
- 招聘人数:1人
- 工作经验:无工作经验
- 学历要求:招1人
- 语言要求:不限
- 职位月薪:4.8-5.5万/月
- 职位类别:集成电路IC设计/应用工程师 IC验证工程师
职位描述
What you do at AMD changes everything
At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, Immersive platforms, and the data center.
Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
PCIE Architect
THE ROLE:
AMD NBIO (North Bridge IO) team delivers industry leading high-performance interconnects IP for all AMD products including dGPU, APU, Server and Game consoles. NBIO global operates seamless from China, North America and Europe.
PCIe is key technology used for internal peripheral connection. This is an exciting opportunity to join AMD’s NBIO team and work on PCIe controller development and deliver to all AMD’s product lines. In this position you will get opportunity to discuss with global architects on feature set, plan strategically and make significant impacts to AMD’s business.
THE PERSON:
Candidate will work as China team PCIe IP architect, currently we’ve 20+ engineers mostly focus on design verification with 10 years industry experience. Candidate need to work with North America PCIe IP architects on industry leading PCIe roadmap planning, system level feature architect and optimize AMD PCIe design for better PPA (Power-Performance-Area). Candidate need to have solid IP design background and outstanding global communication skill.
KEY RESPONSIBILITIES:
- Contribute to AMD PCIe roadmap feature planning
- Drive system level feature architect closure
- Optimize AMD PCIe design for better PPA (Power-Performance-Area).
- Inspiring innovation
- Attend global conference call to present China PCIe team
- Short term global travel upon business need
PREFERRED EXPERIENCE:
- Global company working experience, fluent oral English
· Complex IP/SoC Design, direct experience in IP/SoC or Processor (CPU or GPU) or Industry bus standard (PCIe, USB) is preferred
· Solid knowledge of high-speed IO knowledge (PCIe, USB) is a must
· Solid background with ASIC design flow and multiple ASIC tape out experience
· Knowledge of low power design is a strongly preferred
· Knowledge of Graphics, Display, Multimedia, System Management, Security and/or IO architecture & design is an asset.
· Must have excellent written and verbal communication skills
· Must excel in a dynamic team working environment
· Must be a self-starter and be able to independently drive tasks to completion
ACADEMIC CREDENTIALS:
· MSEE within 8-15 years, or BSEE within 10-20 years’ experience in digital ASIC/SOC design.
LOCATION:
Shanghai/Beijing
公司介绍
联系方式
- Email:bella.yu@amd.com
- 公司地址:上海-浦东新区 张江 环科路669号凯瑞大厦