Sr. Front-end ASIC Design CAD Engineer-Graphics HW
超威半导体(中国)有限公司
- 公司规模:1000-5000人
- 公司性质:外资(欧美)
- 公司行业:电子技术/半导体/集成电路
职位信息
- 发布日期:2012-11-13
- 工作地点:上海
- 招聘人数:若干
- 学历要求:本科
- 职位类别:集成电路IC设计/应用工程师
职位描述
Description of duties in addition to those in job description:
- Understand the FE ASIC design flow, design verification flow, and integration flow.
- Consolidate the design and verification methodologies for graphics and micro-processor hardware.
- Develop infrastructure and release for variant IP/SOC teams.
- Explore the advanced design and verification methodologies for high efficient R&D.
Preferred Experience:
- Good written and fluent oral English
- Graduates from Electrical Engineering (EE) or Computer Science (CS)
- Master with 3+ working experience, or Bachelor with 4+ working experience
- Familiar with Linux Environment (including shell scripting and linux gnu tools)
- Scripting language experience a plus (perl, ruby, tcl, etc.)
- Experience with design verification methodologies (plus)
- Major in EE required:
? 3+ year experience on Verilog HDL coding and debugging
? 2+ year experience on c/c++
? Familiar with SystemVerilog
- Major in CS required:
? 3+ year experience on c/c++
? 1+ year experience on Verilog HDL coding and debugging (plus)
? Familiar with SystemVerilog or SystemC (plus)
- Understand the FE ASIC design flow, design verification flow, and integration flow.
- Consolidate the design and verification methodologies for graphics and micro-processor hardware.
- Develop infrastructure and release for variant IP/SOC teams.
- Explore the advanced design and verification methodologies for high efficient R&D.
Preferred Experience:
- Good written and fluent oral English
- Graduates from Electrical Engineering (EE) or Computer Science (CS)
- Master with 3+ working experience, or Bachelor with 4+ working experience
- Familiar with Linux Environment (including shell scripting and linux gnu tools)
- Scripting language experience a plus (perl, ruby, tcl, etc.)
- Experience with design verification methodologies (plus)
- Major in EE required:
? 3+ year experience on Verilog HDL coding and debugging
? 2+ year experience on c/c++
? Familiar with SystemVerilog
- Major in CS required:
? 3+ year experience on c/c++
? 1+ year experience on Verilog HDL coding and debugging (plus)
? Familiar with SystemVerilog or SystemC (plus)
公司介绍
AMD公司成立于1969年,总部位于美国加利福尼亚州桑尼维尔。AMD(NYSE: AMD)是一家创新的科技公司,致力于与客户及合作伙伴紧密合作,开发下一代面向商用、家用和游戏领域的计算和图形处理解决方案。AMD的业务遍布全球,拥有约为12000名员工。
联系方式
- Email:bella.yu@amd.com
- 公司地址:上海-浦东新区 张江 环科路669号凯瑞大厦