Design Verification engineer (Graphics Front-End)
超威半导体(中国)有限公司
- 公司规模:1000-5000人
- 公司性质:外资(欧美)
- 公司行业:电子技术/半导体/集成电路
职位信息
- 发布日期:2019-11-28
- 工作地点:上海-浦东新区
- 招聘人数:1人
- 工作经验:5-7年经验
- 学历要求:本科
- 职位类别:半导体技术
职位描述
Responsibility:
? Develop micro-architecture for GPU blocks based on architectural requirement.
? Develop RTL code for GPU blocks in Verilog HDL and make sure functional correct and reusable for different configuration.
? Synthesis and deliver netlist that meeting timing, area and power requirement. Help PD on the floorplanning and close timing.
? Analyze gating efficiency report to improve RTL quality
Requirement:
? MS degree of EE with 5+ years working experience in ASIC Company.
? Expert of Verilog RTL design and has experience of large digital ASIC project.
? Familiar with front-end EDA tools and flows.
? Familiar with C/C++ programming and unix/linux and scripts (tcl, perl etc.)
? Fluent English on talking, presentation and writing documents.
? Work is performed with limited supervision. Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager.
? Can solves complex, novel and non-recurring problems; initiates significant changes to existing processes/methods and leads development and implementation
? Possesses specialized knowledge of Computer architecture and computer arithmetic (a plus)
? Possesses specialized knowledge of Computer graphic knowledge (a plus)
职能类别:半导体技术
公司介绍
联系方式
- Email:bella.yu@amd.com
- 公司地址:上海-浦东新区 张江 环科路669号凯瑞大厦