GPU芯片设计资深工程师
超威半导体(中国)有限公司
- 公司规模:1000-5000人
- 公司性质:外资(欧美)
- 公司行业:电子技术/半导体/集成电路
职位信息
- 发布日期:2019-03-29
- 工作地点:上海-浦东新区
- 招聘人数:2人
- 工作经验:10年以上经验
- 学历要求:本科
- 职位类别:集成电路IC设计/应用工程师
职位描述
AMD UMC team is delivering Unified Memory Controller IP (UMC IP) for all AMD projects. It covers design, verification, implementation and post silicon bring-up work for UMC IP.
UMC DV team is responsible to verify the UMC IP mainly, and you'll be working with the global UMC team on IP level and SoC level verification.
RESPONSIBILITIES:
- Fully understand the architecture of the chip and functional block being designed.
- Compose UMC IP/SOC level test plan and validation vectors to ensure functional completeness and correctness. Strong testcase developing and debugging ability is required.
- Develop verification environments/components for UMC IP/SOC level testing.
- Closely working with Design/Architecture/Circuit/SOC team to identify the Milestones and Quality metrics of the project that includes scoping, tracking and delivery.
- Participate in peer reviews of projects.
- Be responsible to mentor and coach the team for greater technical depth in Functional areas as well as the verification methodology improvement and Infrastructure enhancements to support the design environment.
REQUIREMENTS:
· Expert in high level verification flow such as SV, UVM, etc as well as knowledge of industry standard tools for verification.
· Expert in Verification methodology and concepts.
· Expert in design for verification (assertion based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.)
· Expert in Pre-Silicon design process from Architecture, Design, Synthesis and Gate level Implementation till Tapeout release.
· Familiar with Linux Environment (including shell scripting and linux GNU tools)
· Advanced programming knowledge on Verilog and/or C/C++, perl, PLI, Makefile.
· Strong problem solving skills.
· Excellent communication skills (both written and oral) and should be able to participate cross functional engineering teams geographically.
· Good team work spirit.
· Familiar with DRAM including SDDR3/DDR4/GDDR5/HBM/LPDDR is a plus.
· Experience on Memory Controller or high speed interface design is a plus.
EDUCATION:
BS + 9 years or MS + 7 years or PhD + 5 years
Generates publication(s) relevant to areas of expertise
职能类别: 集成电路IC设计/应用工程师
公司介绍
联系方式
- Email:bella.yu@amd.com
- 公司地址:上海-浦东新区 张江 环科路669号凯瑞大厦