苏州招聘

RESPONSIBILITIES:

· Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation

· Perform Synthesis and netlisting tasks such as SDC Development, Scan Insertion, ECO implementation, Formal Verification, etc.

· Work with Physical Design team on Floorplan, budgeting, timing closure, signal integrity, ECO flows, Power analysis, etc.

· Resolve formality, leda, CDC, connectivity and repeater issue.

· Analyze gating efficiency report to improve RTL quality and optimize power.

REQUIREMENTS:

· Have in depth knowledge of entire design process from Design specification, defining architecture, micro-architecture, RTL design and functional verification, synthesis, Physical Design, Timing closure, Tape-out, and post-Si debug.

· Should have expertise in: Cadence RTL Compiler, Design Compiler, PrimeTime, Conformal LEC..

· Some Physical Design exposure required.

· Some exposure to DFT is a strong plus.

· Expertise in script (Perl, Tcl) is a must.

· Should be able to work closely with RTL Designers and Backend Physical Design teams across multiple sites.

· Must have good communication & Analytical thinking skills.

EDUCATION:

· Master with at least 5 years or Bachelor with at least 8 years working experience in ASIC area

AMD公司成立于1969年，总部位于美国加利福尼亚州桑尼维尔。AMD（NYSE: AMD）是一家创新的科技公司，致力于与客户及合作伙伴紧密合作，开发下一代面向商用、家用和游戏领域的计算和图形处理解决方案。AMD的业务遍布全球，拥有约为12000名员工。