MTS. AISC Design/Verification Engineer - SMU
超威半导体(中国)有限公司
- 公司规模:1000-5000人
- 公司性质:外资(欧美)
- 公司行业:电子技术/半导体/集成电路
职位信息
- 发布日期:2019-03-29
- 工作地点:上海-浦东新区
- 招聘人数:若干人
- 工作经验:无工作经验
- 学历要求:招若干人
- 语言要求:不限
- 职位类别:集成电路IC设计/应用工程师
职位描述
MTS. AISC Design/Verification Engineer - SMU
What you do at AMD changes everything
At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center.
Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
AMD System Management Unit (SMU) IP team develops differentiated system management IP for all AMD products. Our team in Shanghai is a critial part of the global SMU team. Many of the SMU features are developped and delivered by the team in Shanghai.
RESPONSIBILITIES:
· Be responsile for System Management IP design. Focus on one or multiple areas including (but not limited to): chip reset and bootcode, security, power management (power-gating, voltage island etc), Network on Chip (NOC), Clocking, platfrom IOs (GPIO, SPI, I2C, etc), data compression engine and DMA, OTP/FUSE, thermal solution, etc.
· Work with RTL designer to get a full deep insight on the design under test, develop stressful testplan
· Build testbench, Create testcase to ensure maximum coverage
· Develop test library, UVC, checkers, to enable multiple level TB reuse
· Integrate the IPs to SOC, bring-up functionatiliy in the SOC
·
REQUIREMENTS:
· Familiar with Verilog HDL, Shell, Perl programming
· Experience with design for verification (assertion based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.)
· Should be versatile in any one of the high level verification flow such as SV,VMM,VERA,OVM etc as well as knowledge of industry standard tools for verification\
· Should have excellent communication skills (both written and oral)
· Strong problem solving skills
· Good communication skill and technical leadership are big plus
·
EDUCATION:
· Master with at least 5 years or Bachelor with at least 8 years working experience in ASIC area
职能类别: 集成电路IC设计/应用工程师
公司介绍
联系方式
- Email:bella.yu@amd.com
- 公司地址:上海-浦东新区 张江 环科路669号凯瑞大厦