Sr. ASIC/ Layout Design Engineer - Verification
超威半导体(中国)有限公司
- 公司规模:1000-5000人
- 公司性质:外资(欧美)
- 公司行业:电子技术/半导体/集成电路
职位信息
- 发布日期:2018-03-12
- 工作地点:北京
- 工作经验:3-4年经验
- 学历要求:本科
- 语言要求:英语熟练
- 职位类别:IC验证工程师 集成电路IC设计/应用工程师
职位描述
JOB DESCRIPTION
1. Create and maintain environment for each projects.
2. Write test scenarios according to AMD or industry spec including USB/SATA/AXI etc.
3. Making test plan, verification plan for projects.
4. Build and optimize verification flow using scripts.
REQUIREMENT
1. Master with at least 4 years or Bachelor with at least 6 years working experience in ASIC area
2. Knowledge on verilog/system verilog is required.
3. Knowledge on verification methodologies such as UVM/OVM is a big plus.
4. Excellent study ability and strong sense of responsibility is required.
5. Good teamwork spirit and communication skills.
6. Good oral and read/write English skills.
职能类别: IC验证工程师 集成电路IC设计/应用工程师
关键字: UVM, 前端验证,
公司介绍
联系方式
- Email:bella.yu@amd.com
- 公司地址:上海-浦东新区 张江 环科路669号凯瑞大厦