SMTS DV Engineer(NBIO) (职位编号:TG)
超威半导体(中国)有限公司
- 公司规模:1000-5000人
- 公司性质:外资(欧美)
- 公司行业:电子技术/半导体/集成电路
职位信息
- 发布日期:2017-07-24
- 工作地点:上海-浦东新区
- 招聘人数:若干人
- 工作经验:8-9年经验
- 学历要求:本科
- 职位类别:IC验证工程师
职位描述
职位描述:
AMD NBIO (North Bridge IO) team delivers industry leading high performance interconnects IP for all AMD products including dGPU, APU, Server and Game consoles. You'll be working with the global team on NBIO subsystem level verification
Responsibility:
* Work with architecture/IP designers to get a full deep insight on the design under test
* Subsystem level test plan development
* Subsystem level test bench develop/setup/maintain, methodology deployment, verification component create/maintain
* Cooperation with Global team(MKDC, HDL) team, Technical lead of the the team
Requirement:
1. Complex IP/ASIC/SOC Design Verification, direct experience in IP/SOC or Processor (CPU or GPU) or Industry bus standard (PCI-e, HT, USB, DDR, DisplayPort) or multimedia/video is preferred.
2.Good knowledge of SystemVerilog and UVM
3.Good knowledge of Verilog/C/C++/System C/SystemVerilog.
4.Verification insights into random techniques.
5.Verification of large scale ASICs.
6.Experience in power verification is an asset.
7.Verification of Virtualization Components is an asset.
8.Strong C and C++ software development and scripting languages (Perl, C Shell, Makefile, …) experience.
9.Solid background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA).
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AMD NBIO (North Bridge IO) team delivers industry leading high performance interconnects IP for all AMD products including dGPU, APU, Server and Game consoles. You'll be working with the global team on NBIO subsystem level verification
Responsibility:
* Work with architecture/IP designers to get a full deep insight on the design under test
* Subsystem level test plan development
* Subsystem level test bench develop/setup/maintain, methodology deployment, verification component create/maintain
* Cooperation with Global team(MKDC, HDL) team, Technical lead of the the team
Requirement:
1. Complex IP/ASIC/SOC Design Verification, direct experience in IP/SOC or Processor (CPU or GPU) or Industry bus standard (PCI-e, HT, USB, DDR, DisplayPort) or multimedia/video is preferred.
2.Good knowledge of SystemVerilog and UVM
3.Good knowledge of Verilog/C/C++/System C/SystemVerilog.
4.Verification insights into random techniques.
5.Verification of large scale ASICs.
6.Experience in power verification is an asset.
7.Verification of Virtualization Components is an asset.
8.Strong C and C++ software development and scripting languages (Perl, C Shell, Makefile, …) experience.
9.Solid background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA).
职能类别: IC验证工程师
公司介绍
AMD公司成立于1969年,总部位于美国加利福尼亚州桑尼维尔。AMD(NYSE: AMD)是一家创新的科技公司,致力于与客户及合作伙伴紧密合作,开发下一代面向商用、家用和游戏领域的计算和图形处理解决方案。AMD的业务遍布全球,拥有约为12000名员工。
联系方式
- Email:bella.yu@amd.com
- 公司地址:上海-浦东新区 张江 环科路669号凯瑞大厦