Sr. Eng for EAD- Memory tuning and Debug (职位编号：MM)
超威半导体（中国）有限公司
- 公司规模：1000-5000人
- 公司性质：外资(欧美)
- 公司行业：电子技术/半导体/集成电路
职位信息
- 发布日期：2017-07-19
- 工作地点：上海-浦东新区
- 招聘人数：若干人
- 职位类别：高级硬件工程师 集成电路IC设计/应用工程师
职位描述
职位描述：
JOB DESCRIPTION
Processor silicon DDR interface electrical test and debug engineer. In this role, this senior level engineer will be part of a highly technical team that develops test plans, executes bring-up & test plans, & debugs electrical issues in the memory sub-system of new processors. The job entails extensive hands-on lab work as well as technical leadership and communication across teams.
DESCRIPTION OF DUTIES
1) Provides DDR technical leadership in the development of new test & validation features
2) Closely interacts with silicon design (DRAM controller and phy) in test execution & debug, as well as in feature definition for future product generation
3) Writes comprehensive electrical & functional test plans for the memory validation of processors
4) Executes electrical & functional test plans for AMD processors using hardware & software validation tools, oscilloscopes, & logic analyzers.
5) Debug of electrical & functional issues of the memory sub-system of new processors
6) Provides detailed input into the platform definition & review of platform designs used in the silicon validation of new processors.
7) Provides technical guidance and training to less experienced engineers and technicians in the planning, test, & debug of the memory sub-system.
SKILLS REQUIRED
1) BS-EE / BS-CE with at least 5 years directly related experience. An advanced degree will be considered a plus.
2) Requires experience and demonstrated technical expertise in the development & execution of platform level electrical & functional test plans. DDR3/4 Memory test experience on electronic components such as uProcessors would be considered a big plus.
3) Requires extensive hands-on experience and demonstrated technical expertise in the debug of I/O interfaces such as DDR
4) Demonstrated experience with or knowledge using oscilloscopes, reading schematics and layout documentation
5) Requires good written and oral communication skills.
6) Demonstrated ability to communicate with a variety of engineering disciplines and management.
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JOB DESCRIPTION
Processor silicon DDR interface electrical test and debug engineer. In this role, this senior level engineer will be part of a highly technical team that develops test plans, executes bring-up & test plans, & debugs electrical issues in the memory sub-system of new processors. The job entails extensive hands-on lab work as well as technical leadership and communication across teams.
DESCRIPTION OF DUTIES
1) Provides DDR technical leadership in the development of new test & validation features
2) Closely interacts with silicon design (DRAM controller and phy) in test execution & debug, as well as in feature definition for future product generation
3) Writes comprehensive electrical & functional test plans for the memory validation of processors
4) Executes electrical & functional test plans for AMD processors using hardware & software validation tools, oscilloscopes, & logic analyzers.
5) Debug of electrical & functional issues of the memory sub-system of new processors
6) Provides detailed input into the platform definition & review of platform designs used in the silicon validation of new processors.
7) Provides technical guidance and training to less experienced engineers and technicians in the planning, test, & debug of the memory sub-system.
SKILLS REQUIRED
1) BS-EE / BS-CE with at least 5 years directly related experience. An advanced degree will be considered a plus.
2) Requires experience and demonstrated technical expertise in the development & execution of platform level electrical & functional test plans. DDR3/4 Memory test experience on electronic components such as uProcessors would be considered a big plus.
3) Requires extensive hands-on experience and demonstrated technical expertise in the debug of I/O interfaces such as DDR
4) Demonstrated experience with or knowledge using oscilloscopes, reading schematics and layout documentation
5) Requires good written and oral communication skills.
6) Demonstrated ability to communicate with a variety of engineering disciplines and management.
职能类别： 高级硬件工程师 集成电路IC设计/应用工程师
公司介绍
AMD公司成立于1969年，总部位于美国加利福尼亚州桑尼维尔。AMD（NYSE: AMD）是一家创新的科技公司，致力于与客户及合作伙伴紧密合作，开发下一代面向商用、家用和游戏领域的计算和图形处理解决方案。AMD的业务遍布全球，拥有约为12000名员工。
联系方式
- Email：bella.yu@amd.com
- 公司地址：上海-浦东新区 张江 环科路669号凯瑞大厦