苏州招聘

Responsibilities:

1.Compose the verification plan according to the chip specification and customer's use cases;
2.Adopt the advanced verification methodologies to create the whole verification environment from scratch
according to the requirements of specific IC;
3.Design Behavioral functional model and test;
4.benches with C/System C, Verilog/System Verilog and script languages
5.Create, build and implement test cases with high degree of accuracy to verify Device Under Test
6.Work closely with concept architect and RTL designer to verify RTL design through extensive test-bench
simulation for modular and top-level design to obtain very high percentage of functional and code coverage
7.Work closely with FPGA prototyping application and validation engineers to verify functional design
8.Coach the inexperienced engineers in the team
9.Secondary task may include design of digital logic with high-level description language (VHDL/Verilog) from specification.

Requirements:
1.Master's/Bachelor's Degree in Electrical/Electronics or Computer Engineering.
2.5+ years IC verification experience on the complex ASIC/SOC
3.Experience with advanced verification methodologies(VMM, OVM, etc.) including functional coverage
and constrained random testing
4.Good knowledge of C, SystemC, and at least one of script languages: Perl, Python, etc.
5.Expert knowledge of VHDL/Verilog HDL and CAD tools (Synopsys and/or Cadence)
6.Team-work spirit, and with a strong drive to excel
7.Able to work independently on a given assignment and work hard to finish on time
8.Good written and communication skills
9.Previous experience on data network communication IC is an added advantage.


Email:szzy0918@gmail.com

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