MTS/SMTS Engineer for Design Verification (职位编号:MM)
超威半导体(中国)有限公司
- 公司规模:1000-5000人
- 公司性质:外资(欧美)
- 公司行业:电子技术/半导体/集成电路
职位信息
- 发布日期:2016-11-24
- 工作地点:北京
- 招聘人数:若干人
- 工作经验:8-9年经验
- 学历要求:本科
- 语言要求:英语 精通
- 职位类别:IC验证工程师
职位描述
职位描述:
Responsibilities:
- Work closely with the SoC design team on understanding the CPU/APU system features being designed;
- Develop and execute test plans for system level functional features related to Memory Controller/ Power Management/ Coherency / Security / Multi-Media …etc.
- Design, implement and improve verification testbench in Verilog, System-Verilog, C/C++, OVM;
- Develop and refine test libraries, model and test cases;
- Apply functional coverage/assertion into testbench as enhancement;
Requirements:
- Minimum 7+ years design verification experiences, at least have 3+ years of DV experience at SOC level
- Strong experience on building system level testbench from scratch
- Very good understanding on verilog, systemverilog, c, c++, Pli, Dpi, Perl
- Rich background on OVM/UVD methodology is a big plus
- Know well about the testbench automation and able to speed up the verification progress using script
- At least 1 complete production cycle from concept to mass production
- Management skill-set for small team
- Be fluent in English speaking and writing
- Good communication skills, strong interpersonal skills and the flexibility
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Responsibilities:
- Work closely with the SoC design team on understanding the CPU/APU system features being designed;
- Develop and execute test plans for system level functional features related to Memory Controller/ Power Management/ Coherency / Security / Multi-Media …etc.
- Design, implement and improve verification testbench in Verilog, System-Verilog, C/C++, OVM;
- Develop and refine test libraries, model and test cases;
- Apply functional coverage/assertion into testbench as enhancement;
Requirements:
- Minimum 7+ years design verification experiences, at least have 3+ years of DV experience at SOC level
- Strong experience on building system level testbench from scratch
- Very good understanding on verilog, systemverilog, c, c++, Pli, Dpi, Perl
- Rich background on OVM/UVD methodology is a big plus
- Know well about the testbench automation and able to speed up the verification progress using script
- At least 1 complete production cycle from concept to mass production
- Management skill-set for small team
- Be fluent in English speaking and writing
- Good communication skills, strong interpersonal skills and the flexibility
职能类别: IC验证工程师
公司介绍
AMD公司成立于1969年,总部位于美国加利福尼亚州桑尼维尔。AMD(NYSE: AMD)是一家创新的科技公司,致力于与客户及合作伙伴紧密合作,开发下一代面向商用、家用和游戏领域的计算和图形处理解决方案。AMD的业务遍布全球,拥有约为12000名员工。
联系方式
- Email:bella.yu@amd.com
- 公司地址:上海-浦东新区 张江 环科路669号凯瑞大厦