上海招聘

Staff Verification Engineer
Location: Shanghai office

Qualifications
-MS in EE/CS/ME.
-Minimum of five years experience.
-Additional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.
-Candidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology.
-Candidate should be familiar with industry standard ASIC design and verification tools and flow.
-Good knowledge DDR protocol and computer system achitecture would be an added advantage.
-Good knowledge of Perl and shell programming would be an added advantage.


Responsibilities:
-Understanding the expected functionality of designs.
-Developing testing and regression plans.
-Designing and developing verification environment.
-Running RTL and gate-level simulations/regression.
-Code/functional coverage development, analysis and closure.

Requirements:
Experience & Skill: 5 Years
-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
-Knowledge in ASIC/FPGA design process and verification tools.
-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
- Scripting and automation skills (tcl, perl, makefile etc) a plus.
-Familiar with C/C++.
-Knowledge of DDR protocol a plus.
-Independent and self-managing.

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