上海招聘

Responsibilities:

· Responsible for 10G+ High Speed SI solutions for Next Generation telecommunications equipment in the IP router.

· Responsible for the backplane architecture design. Design and analysis of high speed serial links for Backplane and chip to chip interfaces. Optimize design performance and manufacturability

· Responsible for board level and system level signal integrity analyze, making design rule and constrains, review the PCB layout design.

· Responsible for 2D, 3D and channelize analyze simulation

· Responsible for high speed board and system signal integrate verification.

· Cooperate with FPGA, PCB and System engineers to analyze and solve the problem in products

Qualifications/Requirements:

· Must have significant, recent signal integrity, backplane and SerDes experience.

· Knowledgeable in using most major SI/PI tools: HFSS, CST, HSPICE, Sigrity Tools, StatEye, ADS, Matlab, Cadence Allegro and APD, HSPICE, and other tools.

· Experience of using oscilloscopes, TDRs, VNAs, BertScope to perform measurements to collect data for design validation and simulation correlations.

· Self-motivated with strong communication and teamwork skills.

· Good at English reading, writing and communication

· Experience in Core router, Edge router or similar product, in large telecomm company.

· MSEE or PhD with 5 years of experience in signal integrity area.

To apply this position, please visit

https://performancemanager12.successfactors.eu/sfcareer/jobreqcareer?jobId=9623&company=Ericsson&username=

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