上海招聘

数字后端经理 Physical design manager、Leader/staff engineer ：
这个是带团队的，需要技术和项目管理团队管理都结合的职位

1. lead soc design team;
2. be able to interface &communicate with internal colleague and external customer;
3. be able to provide design guidance and instruction to engineers;
4. be able to hands-on work on Top level/block level physical design independently

JR:
1. minimum of 5 yrs of working experience;
2. master degree of EE or related field is preferred;
3. team leader or functional leader experience is preferred;
4. familiar with either Synopsys or Cadence design flow and EDA tools;
5. fluent in both Chinese and English


后端设计验证 经理
职位职能: 集成电路IC设计/应用工程师
职位描述:

工作地点：上海
职责概述 :
SOC后端设计和验证
- 参与IC设计布局布线, STA等环节的环境和流程维护
- 从事后端设计从netlist到GDSii的实现
- 编写相关脚本或约束，进行布局布线，时钟树生成，物理验证，功耗/电压降分析, 寄生参数提取等
- 产生并分析运行报告并给出解决方法

专业背景要求:
- 电子工程、计算机科学或相关学科本科3年、硕士3年以上工作经验
- 熟悉IC设计流程和常识，特别是当前流行的后端设计流程
- 熟练使用下面一种或几种EDA开发工具
- 擅长IC版图规划，电源规划，布局布线，时钟树生成、DRC/LVS经验者优先；有一些定制设计和模拟IP
使用经验者优先；有功耗分析电压降分析经验者优先；有串扰和信号完整性分析经验者优先
- 有90nm或65nm或.13工艺成功流片经历


综合素质要求:
- 良好的沟通能力和团队合作精神
- 高度的责任心和敬业精神
- 较强的逻辑思维能力，善于发现问题，具有良好的自学能力和解决问题的能力
- 英语熟练应用。
-本专业优先。


下面的职位要求，有其中之一最好没有也不强调：
1. Responsible for all aspects of physical design and implementation of integrated circuits and other ASIC.
2. Responsibilities include: Participating in the efforts in establishing CAD and physical design methodologies;
3. Focusing on full chip layout planning (partitioning, planning clock distribution and other structure, methodology);
4, Chip floor plan; Power/clock distribution;
5. Chip assembly and P&R; Timing closure;
6. Power and noise analysis;
7. Back-end verification across multiple projects;


Requirements:
1. BSEE 5+years,MSEE 3+years experience in large VLSI physical design implementation;
2. Successful track record of delivering products to production is a must;
3. Understanding of custom Macro blocks such as RAMs, PLLs, high-speed IO drivers;
4. Prior experience in Timing closure, clock/power Distribution and analysis, RC Extraction and correlation, place and route and tapeout issues;
5. Working knowledge of deep sub-micron routing issues as they relate to power and timing;
6. Circuit level comprehension of time critical paths. Spice experience a plus;
7. Should be a power user of Apollo/Astro for routing, PhysOpt (Physical Compiler) for placement, PrimeTime for Timing Verification, dc_shell etc.


PR Engneer


Responsibilities:
1. Layout database creation : layout library and Milkyway database creation;
2. Initial floorplan : Initial chip or subchip level floorplan;
3. Place & Route: Perform cells placement; Perform global route and detail route;
4. DRC/LVS corrections; Layout script creation: Create script to perform layout modification;
5. Create Apollo scheme file to maintain and update Apollo database;
6. Layout modification: Follow signal integration report to perform necessary modification;
7. Requirements: Bachelor Degree or higher in EE major;
8. 0-3 years P&R working experience;
9. Knowledge about Solaris/Unix/Linux operating system; Good command of English in both written and oral format.


DFT Engineer
1. Responsibilities: Synthesis: Use DC (Design Compiler), ACS (Advanced Chip Synthesis), and PC (Physical Compiler) for chip synthesis either from RTL code or Gate level netlist;


2. Static Timing analysis and Formal verification: Perform timing analysis and timing optimization;
3. Run formal verification after each ECO and timing optimization;


4. DFT design: Scan chain insertion; JTAG/Boundary scan insertion; NAND tree insertion;


5. Memory BIST insertion; Logic BIST insertion;
6. Test pattern generation and simulation: ATPG test vector generation and pattern simulation;
7. Fault grading test vector generation;
8. Memory BIST simulation; JTAG/NAND tree simulation;
9. Test vectorl format conversion and provide all test related patterns to test and product engineers;
10. Requirements: BS, MS preferred; 0-3 years working experience on chip integration;
11. Strong Logic design and Semiconductor device physic background; Good English in both written and spoken.


简历发jinjuan@raiserf.com

射频主管

背景要求：

1、 大学本科微波或射频专业，十年以上相关工作经验，或者硕士微波或射频专业，六年以上相关工作经验，或者微波或射频专业博士毕业, 五年以上工作经验，经历过从概念设计到量产的全过程，

2、 愿意投身射频测量仪器，追求完美的工程质量，对新知识有强烈的求知欲，

3、 在现有担任过射频主管职位，

4、 研发过矢量网络分析仪的优先。

目前的研发工作内容是：

1、研发天馈线分析仪

2、矢量网络分析仪等

职责范围：

1，负责产品定义，和市场销售部门紧密配合制定三年至五年期产品路线图；

2， 负责射频仪器设计团队建设和招聘，负责掌握模拟设计团队的上千万数量级的研发成本预算；

3，负责模拟射频模块设计和验证的审核制度，对最终产品成败负责；

4，负责对多个项目进行人员资源的调配，监督项目进度；

5，开发射频系统架构，参考模型，测试计划，测试环境等一整套工作流程；

6，动线路调试以保证功能的正确和性能的优越；

7，参与产品定型与转产的测试；

8，负责与EDA 厂商合作确定软件购买，新工具的采用等。

技能要求：

1，熟悉天线理论及制作工艺；

2，对于模拟和射频电路结构设计和性能测试有具体的实践经验；

3， 对于模拟，混合信号和射频电路模块的几个关键点有独立的设计能力，比如电压比较器，模数转换器，放大器，低噪声放大器，混频器，锁相环，电源管理模块，参考电压模块等等 ；

4，熟悉射频分析的专业用软件；

5，超强的书面和口头沟通能力；

6，可以进行脚本编写，Perl, UNIX Shell, Python等等；

7，熟练英语阅读、听说和文档写作技能；

8，具有很强的创新理念，解决问题的能力，和与中外同事有良好的团队合作精神。

Confidential

ASIC Design Engineer

Job Description

You will be working with internal and external customers to develop state of the art IC solutions utilizing && leading edge CMOS cell-based ASIC technologies. You will have responsibility for ASIC designs through all of the key development and implementation phases including RTL analysis, synthesis, design optimization, timing verification, simulation, test insertion, physical design, vector generation, and post-prototype test support. Candidates will have opportunity to work on the latest 40nm/28nm designs.

Detail design tasks include

- Presales support (die size support, memory generation, addressing customer questions and concerns.)

- RTL analysis & synthesis

- Top level and block level physical design Implementation (bonding, floor planning, power structure insertion, place and route, timing closure)

- Test structure insertion/silicon testing debug

- Formal verification

- Static timing analysis

- Cross talk analysis

- Power verification

- Physical verification

- Overtime, candidates are expected to develop the most of above skills. Candidates who have the desire to seek the in-depth and broad technical challenge should apply.

Requirements/Qualifications (Education)

Education: BS/MS Electrical, Computer Engineering or Equivalent

- 2+ years experience in ASIC design and implementation. Familiar with all aspects of ASIC design implementation flow and specializing in physical design or DFT implementation. The ideal candidate should have successfully completed at least one mid-size ASIC or ASSP tapeout.

- Experience with Synopsys Astro or ICC is a plus. Other physical design tool experience will also be considered. Scripting skill is a strong plus.

- Experience in debugging prototypes considered a strong plus. Knowledge and hands on use of test insertion / vector generation / verification a plus. Some experience with Signal integrity a bonus.

- Experience in working with customers is desired. Must possess excellent communication skills and strong self-motivation. Be able to effectively communicate with other members of the design team, supporting organizations, and management. This position requires frequent interface with customers

- Candidates have ONE OR MORE good skill sets of the following areas are highly encouraged to apply:

- RTL Analysis/Synthesis/STA: The ideal candidate should have strong skills for the front-end of design

- implementation which includes RTL Analysis, Synthesis Strategies, and STA setup for complex ASIC

- environments. This would include strategies for power management.

- OR

- Physical Design Implementation: The ideal candidate should be strong in the Physical Design (at least at block level) which includes floor planning, design closure, & STA. Having strong DRC & LVS skills are a plus. Strong

- Synopsys Astro/ICC experience a plus. Having Mentor Calibre skills a plus.

- OR

- Physical Verification: The ideal candidate should have in-depth understanding of transistor level IC fabrication process, familiar with major foundries(TSMC or SMIC) runsets and verification flow, custom layout experience is a plus, successfully done LVS/DRC/ERC/Antenna check for multiple tapeouts is a strong plus. Understanding of DFM is a plus. Calibre experience is a plus.

- OR

- DFT: The ideal candidate should be strong in all DFT (Design for Test) for all aspects. This would include

- scan/TDF, TestKompress, MEMBIST/BISR, JTAG and etc. Having STA skills is a plus for all aspects of test. Responsible for support / debug of customer designs after delivery of prototypes

       上海中科睿射电子科技有限公司是一家依托中国科学院上海高等研究院，由中科院上海高等研究院和风险投资机构共同投资的高科技企业。
       中科睿射专注于移动无线通信射频前端芯片、模块的设计和制造。我们的技术源于美国硅谷，研发团队由国际知名的无线射频集成电路设计专家领衔创建，汇聚了多位各属专长的博士、硕士组成。技术方面在经过属于自己知识产权的发明创造而提升到新的高度。
       目前公司的产品有无线终端的射频功率放大器（RF PA）、低噪声放大器（LNA）、开关（Switch）以及各种射频前端组件（FEM），它们应用于Wifi、Wimax、TD-LTE、CDMA、Zigbee、Bluetooth和GSM等平台，具广阔的应用前景和市场潜力。